Re: [PATCH v4 59/65] accel: Always register AccelOpsClass::get_virtual_clock() handler

> On 2 Jul 2025, at 20.53, Philippe Mathieu-Daudé wrote: > > In order to dispatch over AccelOpsClass::get_virtual_clock(), > we need it always defined, not calling a hidden handler under > the hood. Make AccelOpsClass::get_virtual_clock() mandatory. > Register the default cpus_kick_thread() for

Re: [PATCH v6 02/39] system/memory: Restrict eventfd dispatch_write() to emulators

Xiaoyao Li writes: > On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote: >> Commit 8c56c1a592b ("memory: emulate ioeventfd") added a !KVM >> check because the only accelerator available back then were TCG, >> QTest and KVM. Then commit 126e7f78036 ("kvm: require >> KVM_CAP_IOEVENTFD and KVM_CAP_IO

Re: [PATCH] hmp-cmds-target.c: add CPU_DUMP_VPU in hmp_info_registers()

On 23/6/25 16:53, Daniel Henrique Barboza wrote: Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be logged by log_cpu_exec() in TCG. This flag was then used in commit b227f6a8a7 to print RISC-V vector registers using this flag. Note that this change was done in riscv_cpu_dum

[PULL 04/31] accel/tcg: Remove 'info opcount' and @x-query-opcount

Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER", released with QEMU v8.1.0) we get pointless output: (qemu) info opcount [TCG profiler not compiled] Remove that unstable and unuseful command. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Dr. David Alan Gilbert Reviewed-by:

[PULL 01/31] system/cpus: Assert interrupt handling is done with BQL locked

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-5-phi...@linaro.org> --- accel/tcg/tcg-accel-ops.c | 2 -- system/cpus.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) di

[PULL 06/31] accel/tcg: Factor tcg_dump_flush_info() out

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-10-phi...@linaro.org> --- accel/tcg/monitor.c | 27 +-- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/a

[PULL 07/31] accel/tcg: Factor tcg_dump_stats() out for re-use

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-11-phi...@linaro.org> --- accel/tcg/internal-common.h | 2 ++ accel/tcg/monitor.c | 11 --- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git

[PULL 03/31] accel/kvm: Reduce kvm_create_vcpu() declaration scope

kvm_create_vcpu() is only used within the same file unit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-7-phi...@linaro.org> --- include/system/kvm.h | 8 accel/kvm/kvm-all.c | 8 +

[PULL 05/31] accel/tcg: Remove profiler leftover

TCG profiler was removed in commit 1b65b4f54c7. Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-9-phi...@linaro.org> --- accel/tcg/moni

[PULL 23/31] accel: Propagate AccelState to AccelClass::init_machine()

In order to avoid init_machine() to call current_accel(), pass AccelState along. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Message-Id: <20250703173248.44995-31-phi...@linaro.org> --- include/qemu/accel.h| 2 +- accel/accel-system.c

Re: [PATCH v6 25/39] accel/whpx: Expose whpx_enabled() to common code

On Thu, Jul 03, 2025 at 07:32:31PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:31 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 25/39] accel/whpx: Expose whpx_enabled() to common code > X-Mailer: git-send-email 2.49.0 > > Currently whpx_enabled() is restricted

[PULL 09/31] accel/hvf: Move per-cpu method declarations to hvf-accel-ops.c

hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL), while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-16-phi...@linaro.org> --- accel/hvf/hvf-ac

[PULL 17/31] accel/system: Document cpu_synchronize_state_post_init/reset()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-24-phi...@linaro.org> --- include/system/accel-ops.h | 8 include/system/hw_accel.h | 8 2 files changed, 16 insertions(+) diff --git a/include/system

[PULL 21/31] accel: Expose and register generic_handle_interrupt()

In order to dispatch over AccelOpsClass::handle_interrupt(), we need it always defined, not calling a hidden handler under the hood. Make AccelOpsClass::handle_interrupt() mandatory. Expose generic_handle_interrupt() prototype and register it for each accelerator. Suggested-by: Richard Henderson

[PULL 22/31] accel: Keep reference to AccelOpsClass in AccelClass

Allow dereferencing AccelOpsClass outside of accel/accel-system.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Message-Id: <20250703173248.44995-30-phi...@linaro.org> --- include/qemu/accel.h | 3 +++ include/system/accel-ops.h | 3 ++- a

[PULL 20/31] accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'

'dummy' helpers are specific to accelerator implementations, no need to expose them via "system/cpus.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Message-Id: <20250703173248.44995-27-phi...@linaro.org> --- MAINTAINERS | 1 + accel/

[PULL 00/31] Accelerators patches for 2025-07-04

The following changes since commit c77283dd5d79149f4e7e9edd00f65416c648ee59: Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into staging (2025-07-03 06:01:41 -0400) are available in the Git repository at: https://github.com/philmd/qemu.git tags/accel-2025070

[PULL 26/31] accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250703173248.44995-35-phi...@linaro.org> --- accel/kvm/kvm-all.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 72fba12d9fa..007f82a50de

[PULL 18/31] accel/nvmm: Expose nvmm_enabled() to common code

Currently nvmm_enabled() is restricted to target-specific code. By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-25-phi...@linaro.org> --- MAINTAINERS

[PULL 11/31] cpus: Document CPUState::vcpu_dirty field

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Reviewed-by: Xiaoyao Li Message-Id: <20250703173248.44995-18-phi...@linaro.org> --- include/hw/core/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/inc

[PULL 13/31] accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field

No need for accel-specific @dirty field when we have a generic one in CPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-20-phi...@linaro.org> --- target/i386/nvmm/nvmm-all.c | 21 +

[PULL 15/31] accel/kvm: Remove kvm_cpu_synchronize_state() stub

Since commit 57038a92bb0 ("cpus: extract out kvm-specific code to accel/kvm") the kvm_cpu_synchronize_state() stub is not necessary. Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xi

[PULL 25/31] accel/kvm: Prefer local AccelState over global MachineState::accel

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250703173248.44995-32-phi...@linaro.org> --- accel/kvm/kvm-all.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 264f288dc64..72fba12d9fa 100

[PULL 16/31] accel/system: Document cpu_synchronize_state()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250703173248.44995-23-phi...@linaro.org> --- include/system/accel-ops.h | 8 include/system/hw_accel.h | 13 +++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff

[PULL 24/31] accel/tcg: Prefer local AccelState over global current_accel()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250703173248.44995-33-phi...@linaro.org> --- accel/tcg/tcg-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index d68fbb23773..c674d5bcf78 100644

[PULL 28/31] accel: Remove unused MachineState argument of AccelClass::setup_post()

This method only accesses xen_domid/xen_domid_restrict, which are both related to the 'accelerator', not the machine. Besides, xen_domid aims to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict QOM property. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Mes

[PULL 19/31] accel/whpx: Expose whpx_enabled() to common code

Currently whpx_enabled() is restricted to target-specific code. By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250703173248.44995-26-phi...@linaro.org> --- MAINTAINERS | 1 + inc

[PULL 30/31] MAINTAINERS: Add me as reviewer of overall accelerators section

I'd like to be informed of overall changes of accelerators. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250703173248.44995-40-phi...@linaro.org> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index fca98e1219

[PULL 08/31] accel/hvf: Restrict internal declarations

Common code only needs to know whether HVF is enabled and the QOM type. Move the rest to "hvf_int.h", removing the need for COMPILING_PER_TARGET #ifdef'ry. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-Id: <2025070317

[PULL 29/31] accel: Pass AccelState argument to gdbstub_supported_sstep_flags()

In order to have AccelClass methods instrospect their state, we need to pass AccelState by argument. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250703173248.44995-37-phi...@linaro.org> --- include/qemu/accel.h | 2 +- accel/accel-common.c | 2 +- accel/h

[PULL 31/31] hmp-cmds-target.c: add CPU_DUMP_VPU in hmp_info_registers()

From: Daniel Henrique Barboza Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be logged by log_cpu_exec() in TCG. This flag was then used in commit b227f6a8a7 to print RISC-V vector registers using this flag. Note that this change was done in riscv_cpu_dump_state(), the cpu_

[PULL 27/31] accel: Directly pass AccelState argument to AccelClass::has_memory()

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20250703173248.44995-34-phi...@linaro.org> --- include/qemu/accel.h | 2 +- accel/kvm/kvm-all.c | 4 ++-- system/memory.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/qemu/ac

[PULL 02/31] accel/kvm: Remove kvm_init_cpu_signals() stub

Since commit 57038a92bb0 ("cpus: extract out kvm-specific code to accel/kvm") the kvm_init_cpu_signals() stub is not necessary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Xiaoyao Li Message-Id: <20250703173248.44995-6-phi...@linaro.org> --- accel/stubs/kv

[PATCH 1/2] rust/qemu-api-macros: normalize TryInto output

Remove extraneous `;` and add missing trailing comma to TryInto derive macro to match rustfmt style. We will add a test in the followup commit and we would like the inlined output in the test body to be properly formatted as well. No functional changes intended. Signed-off-by: Manos Pitsidianakis

[PULL 18/40] target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE

From: Daniel Henrique Barboza The SBI spec states, for console write byte: "This is a blocking SBI call and it will only return after writing the specified byte to the debug console. It will also return, with SBI_ERR_FAILED, if there are I/O errors." Being a blocker call will either succeed wri

[PULL 33/40] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

From: Huang Borong <3543977...@qq.com> Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source, high-performance RISC-V processor. More details can be found at: https://github.com/OpenXiangShan/XiangShan Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized bas

[PULL 23/40] hw/riscv/virt: Use setprop_sized_cells for memory

From: Joel Stanley Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20250604025450.85327-4-j...@jms.id.au> Signed-off-by: Alistair F

Re: [PATCH v6 32/39] accel/tcg: Prefer local AccelState over global current_accel()

On Thu, Jul 03, 2025 at 07:32:38PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:38 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 32/39] accel/tcg: Prefer local AccelState over global > current_accel() > X-Mailer: git-send-email 2.49.0 > > Signed-off-by: Philipp

[PULL 10/40] target/riscv: remove capital 'Z' CPU properties

From: Daniel Henrique Barboza These properties were deprecated in QEMU 8.2, commit 8043effd9b. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250530134608.1806922-1-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h

[PULL 39/40] target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction

From: Vasilis Liaskovitis Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1 and rd arguments are x0. In this case, if the new property is true, only the vill bit will be set. See https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding Acco

[PULL 31/40] hw/riscv/virt: Use setprop_sized_cells for iommu

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

[PULL 30/40] hw/riscv/virt: Use setprop_sized_cells for rtc

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

[PULL 34/40] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype

From: Huang Borong <3543977...@qq.com> This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing Signe

[PULL 24/40] hw/riscv/virt: Use setprop_sized_cells for aplic

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

[PULL 22/40] hw/riscv/virt: Use setprop_sized_cells for clint

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

[PULL 26/40] hw/riscv/virt: Use setprop_sized_cells for plic

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

[PULL v2 00/36] Accelerators patches for 2025-07-04

The following changes since commit c77283dd5d79149f4e7e9edd00f65416c648ee59: Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into staging (2025-07-03 06:01:41 -0400) are available in the Git repository at: https://github.com/philmd/qemu.git tags/accel-2025070

Re: [PATCH v6 18/39] accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field

On Thu, Jul 03, 2025 at 07:32:24PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:24 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 18/39] accel/hvf: Replace @dirty field by generic > CPUState::vcpu_dirty field > X-Mailer: git-send-email 2.49.0 > > No need for acc

Re: [PATCH v6 22/39] accel/system: Document cpu_synchronize_state()

On Thu, Jul 03, 2025 at 07:32:28PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:28 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 22/39] accel/system: Document cpu_synchronize_state() > X-Mailer: git-send-email 2.49.0 > > Signed-off-by: Philippe Mathieu-Daudé >

Re: [PATCH v6 24/39] accel/nvmm: Expose nvmm_enabled() to common code

On Thu, Jul 03, 2025 at 07:32:30PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:30 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 24/39] accel/nvmm: Expose nvmm_enabled() to common code > X-Mailer: git-send-email 2.49.0 > > Currently nvmm_enabled() is restricted

Re: [PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

On Tue, Jun 17, 2025 at 4:29 PM ~liuxu wrote: > > Thanks for Alistair's correction on the V8 version. > > Now Zclsd has been disabled for the "max" CPU as C and F are already > enabled. This is still broken with userspace mode: ``` qemu-riscv64: Zclsd cannot be supported together with C and F ex

Re: [PATCH v6 34/39] accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()

On Thu, Jul 03, 2025 at 07:32:40PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:40 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 34/39] accel/kvm: Directly pass KVMState argument to > do_kvm_create_vm() > X-Mailer: git-send-email 2.49.0 > > Signed-off-by: Phili

Re: [PATCH v6 33/39] accel: Directly pass AccelState argument to AccelClass::has_memory()

On Thu, Jul 03, 2025 at 07:32:39PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:39 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 33/39] accel: Directly pass AccelState argument to > AccelClass::has_memory() > X-Mailer: git-send-email 2.49.0 > > Reviewed-by: Ric

Re: [PATCH v6 05/39] accel/kvm: Remove kvm_init_cpu_signals() stub

On Thu, Jul 03, 2025 at 07:32:11PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:11 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 05/39] accel/kvm: Remove kvm_init_cpu_signals() stub > X-Mailer: git-send-email 2.49.0 > > Since commit 57038a92bb0 ("cpus: extract o

Re: [PATCH v6 20/39] accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field

On Thu, Jul 03, 2025 at 07:32:26PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:26 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 20/39] accel/whpx: Replace @dirty field by generic > CPUState::vcpu_dirty field > X-Mailer: git-send-email 2.49.0 > > No need for ac

Re: [PATCH v6 23/39] accel/system: Document cpu_synchronize_state_post_init/reset()

On Thu, Jul 03, 2025 at 07:32:29PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:29 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 23/39] accel/system: Document > cpu_synchronize_state_post_init/reset() > X-Mailer: git-send-email 2.49.0 > > Signed-off-by: Philipp

Re: [PATCH v6 27/39] accel: Pass old/new interrupt mask to handle_interrupt() handler

On Thu, Jul 03, 2025 at 07:32:33PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:33 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 27/39] accel: Pass old/new interrupt mask to > handle_interrupt() handler > X-Mailer: git-send-email 2.49.0 > > Update CPUState::int

[PULL 36/40] migration: Fix migration failure when aia is configured as aplic-imsic

From: "liu.xuem...@zte.com.cn" Address an error in migration when aia is configured as 'aplic-imsic' in riscv kvm vm by adding riscv_aplic_state_needed() and riscv_imsic_state_needed() to determine whether the corresponding sates are needed. Previously, the fields in the vmsds of 'riscv_aplic' a

[PULL 32/40] hw/riscv/virt: Use setprop_sized_cells for pcie

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

Re: [PATCH v6 34/39] accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()

On Thu, Jul 03, 2025 at 07:32:40PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:40 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 34/39] accel/kvm: Directly pass KVMState argument to > do_kvm_create_vm() > X-Mailer: git-send-email 2.49.0 > > Signed-off-by: Phili

[PULL 25/40] hw/riscv/virt: Use setprop_sized_cells for aclint

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

[PULL 19/40] target/riscv: Fix fcvt.s.bf16 NaN box checking

From: Anton Blanchard fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16 quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN. Signed-off-by: Anton Blanchard Acked-by: Alistair Francis Message-ID: <20250501114253.594887-1-ant...@tenstorrent.com> Signed-off-by: Alista

[PULL 28/40] hw/riscv/virt: Use setprop_sized_cells for reset

From: Joel Stanley The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-

Re: [PATCH v6 35/39] accel: Remove unused MachineState argument of AccelClass::setup_post()

On Thu, Jul 03, 2025 at 07:32:41PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:41 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 35/39] accel: Remove unused MachineState argument of > AccelClass::setup_post() > X-Mailer: git-send-email 2.49.0 > > This method on

Re: [PATCH v6 33/39] accel: Directly pass AccelState argument to AccelClass::has_memory()

On Thu, Jul 03, 2025 at 07:32:39PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:39 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 33/39] accel: Directly pass AccelState argument to > AccelClass::has_memory() > X-Mailer: git-send-email 2.49.0 > > Reviewed-by: Ric

[PULL 20/40] hw/char: sifive_uart: Avoid infinite delay of async xmit function

From: Florian Lugou The current handler for TXFIFO writes schedules an async callback to pop characters from the queue. When software writes to TXFIFO faster than the async callback delay (100ns), the timer may be pushed back while the previous character has not be dequeued yet. This happens in p

[PULL 17/40] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register

From: Nutty Liu The original implementation incorrectly performed a bitwise AND operation between the PPN of iova and PPN Mask, leading to an incorrect PPN field in Translation-reponse register. The PPN of iova should be set entirely in the PPN field of Translation-reponse register. Also remove

[PULL 37/40] target/riscv: Fix MEPC/SEPC bit masking for IALIGN

From: Charalampos Mitrodimas According to the RISC-V Privileged Architecture specification, the low bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits must be zero. This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and the implicit reads by MRET/SRET instructi

Re: [PATCH v6 36/39] accel: Pass AccelState argument to gdbstub_supported_sstep_flags()

On Thu, Jul 03, 2025 at 07:32:42PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 3 Jul 2025 19:32:42 +0200 > From: Philippe Mathieu-Daudé > Subject: [PATCH v6 36/39] accel: Pass AccelState argument to > gdbstub_supported_sstep_flags() > X-Mailer: git-send-email 2.49.0 > > In order to have A

[PULL 14/40] target/riscv: support atomic instruction fetch (Ziccif)

From: Jim Shu Support 4-byte atomic instruction fetch when instruction is natural aligned. Current implementation is not atomic because it loads instruction twice for first and last 2 bytes. We load 4 bytes at once to keep the atomicity. This instruction preload method only applys when instructi

[PULL 13/40] target/riscv/cpu.c: do better with 'named features' doc

From: Daniel Henrique Barboza Most of the named features are added directly in isa_edata_arr[], some of them are also added in riscv_cpu_named_features(). There is a reason for that, and the existing docs can do better explaining it. Signed-off-by: Daniel Henrique Barboza Message-ID: <202505292

[PULL 35/40] target/riscv: rvv: Fix missing exit TB flow for ldff_trans

From: Max Chou According to the V spec, the vector fault-only-first load instructions may change the VL CSR. So the ldff_trans TCG translation function should generate the lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to make sure the vl_eq_vlmax TB flag is correct. Signed-

[PULL 01/40] target/riscv: Add the checking into stimecmp write function.

From: Jim Shu Preparation commit to let aclint timer to use stimecmp write function. Aclint timer doesn't call sstc() predicate so we need to check inside the stimecmp write function. Signed-off-by: Jim Shu Acked-by: Alistair Francis Message-ID: <20250519143518.11086-2-jim@sifive.com> Sign

[PULL 38/40] tests/tcg/riscv64: Add test for MEPC bit masking

From: Charalampos Mitrodimas Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an ill

[PULL 40/40] target: riscv: Add Svrsw60t59b extension support

From: Alexandre Ghiti The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Reviewed-by: Deepak Gupta Signed-off-by: Alexandre Ghiti Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8

Re: [PATCH v4 00/11] target/arm: Fix M-profile helper loads/stores alignment checks

On Thu, 3 Jul 2025 at 09:56, William Kosasih wrote: > > Historically, M-profile helper functions in m_helper.c and mve_helper.c > used the unaligned cpu_*_data_ra() routines to perform guest memory > accesses. This meant we had no way to enforce alignment constraints > when executing helper-based

Re: [PATCH 1/5] arm/cpu: store id_afr0 into the idregs array

On 4/7/25 16:19, Cornelia Huck wrote: Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c| 2 +- target/arm/cpu-sysregs.h.inc | 1 + target/arm/cpu.h | 1 - target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 2 +- target/arm/tcg/cpu-v7m.c

Re: [PATCH v2 03/24] migration: Normalize tls arguments

On Fri, Jul 04, 2025 at 10:12:33AM -0300, Fabiano Rosas wrote: [...] > >>> +static void tls_opt_to_str(StrOrNull **tls_opt) > >>> +{ > >>> +StrOrNull *opt = *tls_opt; > >>> + > >>> +if (!opt) { > >>> +return; > >> > >> ... it can also be null. > >> > > > > Hmm, I'll have to double

Re: [PATCH 2/5] arm/cpu: store id_aa64afr{0,1} into the idregs array

On 4/7/25 16:19, Cornelia Huck wrote: Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h.inc | 2 ++ target/arm/cpu.h | 2 -- target/arm/helper.c | 4 ++-- target/arm/tcg/cpu64.c | 16 4 files changed, 12 insertions(+), 12 deletions(-)

Re: [PATCH v2 04/24] migration: Remove MigrateSetParameters

On Mon, Jun 30, 2025 at 04:58:53PM -0300, Fabiano Rosas wrote: > Now that the TLS options have been made the same between > migrate-set-parameters and query-migrate-parameters, a single type can > be used. Remove MigrateSetParameters. > > The TLS options documentation from MigrationParameters were

Re: [PATCH 3/5] arm/cpu: fix trailing ',' for SET_IDREG

On 4/7/25 16:19, Cornelia Huck wrote: While a trailing comma is not broken for SET_IDREG invocations, it does look odd; use a semicolon instead. Fixes: f1fd81291c91 ("arm/cpu: Store aa64mmfr0-3 into the idregs array") Fixes: def3f1c1026a ("arm/cpu: Store aa64dfr0/1 into the idregs array") Signed

Re: [PATCH v2 07/24] migration: Add a flag to track block-bitmap-mapping input

On Mon, Jun 30, 2025 at 04:58:56PM -0300, Fabiano Rosas wrote: > The QAPI converts an empty list on the block-bitmap-mapping input into > a NULL BitmapMigrationNodeAliasList. The empty list is a valid input > for the block-bitmap-mapping option, so commit 3cba22c9ad ("migration: > Fix block_bitmap_

Re: [PATCH v2 05/24] qapi/migration: Don't document MigrationParameter

On Mon, Jun 30, 2025 at 04:58:54PM -0300, Fabiano Rosas wrote: > The MigrationParameter (singular) enumeration is not part of the > migration QMP API, it's only used for nicely converting HMP strings > into MigrationParameters (plural) members and for providing readline > completion. > > Documenti

Re: [PATCH 5/5] arm/kvm: shorten one overly long line

On 4/7/25 16:19, Cornelia Huck wrote: Fixes: 804cfc7eedb7 ("arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays") Signed-off-by: Cornelia Huck --- target/arm/kvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-D

[PULL 21/27] vfio/iommufd: preserve descriptors

From: Steve Sistare Save the iommu and vfio device fd in CPR state when it is created. After CPR, the fd number is found in CPR state and reused. Signed-off-by: Steve Sistare Reviewed-by: Zhenzhong Duan Link: https://lore.kernel.org/qemu-devel/1751493538-202042-16-git-send-email-steven.sist..

[PULL 10/27] migration: cpr_get_fd_param helper

From: Steve Sistare Add the helper function cpr_get_fd_param, to use when preserving a file descriptor that is opened externally and passed to QEMU. cpr_get_fd_param returns a descriptor number either from a QEMU command-line parameter, from a getfd command, or from CPR state. When a descriptor

[PULL 14/27] vfio/iommufd: use IOMMU_IOAS_MAP_FILE

From: Steve Sistare Use IOMMU_IOAS_MAP_FILE when the mapped region is backed by a file. Such a mapping can be preserved without modification during CPR, because it depends on the file's address space, which does not change, rather than on the process's address space, which does change. Signed-of

[PULL 18/27] vfio/iommufd: register container for cpr

From: Steve Sistare Register a vfio iommufd container and device for CPR, replacing the generic CPR register call with a more specific iommufd register call. Add a blocker if the kernel does not support IOMMU_IOAS_CHANGE_PROCESS. This is mostly boiler plate. The fields to to saved and restored

[PULL 24/27] vfio/iommufd: change process

From: Steve Sistare Finish CPR by change the owning process of the iommufd device in post load. Signed-off-by: Steve Sistare Reviewed-by: Zhenzhong Duan Link: https://lore.kernel.org/qemu-devel/1751493538-202042-19-git-send-email-steven.sist...@oracle.com [ clg: Fixed missing "qemu/error-repo

Re: [PATCH v6 00/39] accel: Preparatory cleanups for split-accel

On 3/7/25 19:32, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (39): hw/core/machine: Display CPU model name in 'info cpus' command system/memory: Restrict eventfd dispatch_write() to emulators system/runstate: Document qemu_add_vm_change_state_handler() system/cpus: Assert in

[PULL 08/27] vfio-pci: preserve INTx

From: Steve Sistare Preserve vfio INTx state across cpr-transfer. Preserve VFIOINTx fields as follows: pin : Recover this from the vfio config in kernel space interrupt : Preserve its eventfd descriptor across exec. unmask : Ditto route.irq : This could perhaps be recovered in vfio_pci_p

[PULL 11/27] backends/iommufd: iommufd_backend_map_file_dma

From: Steve Sistare Define iommufd_backend_map_file_dma to implement IOMMU_IOAS_MAP_FILE. This will be called as a substitute for iommufd_backend_map_dma, so the error conditions for BARs are copied as-is from that function. Signed-off-by: Steve Sistare Reviewed-by: Zhenzhong Duan Link: https

[PULL 27/27] vfio: doc changes for cpr

From: Steve Sistare Update documentation to say that cpr-transfer supports vfio and iommufd. Signed-off-by: Steve Sistare Reviewed-by: Cédric Le Goater Reviewed-by: Fabiano Rosas Link: https://lore.kernel.org/qemu-devel/1751493538-202042-22-git-send-email-steven.sist...@oracle.com Signed-off

[PULL 26/27] vfio/container: delete old cpr register

From: Steve Sistare vfio_cpr_[un]register_container is no longer used since they were subsumed by container type-specific registration. Delete them. Signed-off-by: Steve Sistare Reviewed-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/1751493538-202

[PULL 20/27] vfio/iommufd: cpr state

From: Steve Sistare VFIO iommufd devices will need access to ioas_id, devid, and hwpt_id in new QEMU at realize time, so add them to CPR state. Define CprVFIODevice as the object which holds the state and is serialized to the vmstate file. Define accessors to copy state between VFIODevice and Cp

[PULL 22/27] vfio/iommufd: reconstruct device

From: Steve Sistare Reconstruct userland device state after CPR. During vfio_realize, skip all ioctls that configure the device, as it was already configured in old QEMU. Skip bind, and use the devid from CPR state. Skip allocation of, and attachment to, ioas_id. Recover ioas_id from CPR stat

[PULL 04/27] i386/tdx: Build TDX only for 64-bit target

From: Xiaoyao Li Build errors related to TDX were reported when QEMU built on 32-bit host[1][2]. Since TDX cannot work on 32-bit host and it's also not worth supporting TDX with 32-bit QEMU, limit TDX to 64-bit target only. [1] https://lore.kernel.org/qemu-devel/20250602173101.1052983-1-...@red

[PULL 17/27] vfio/iommufd: device name blocker

From: Steve Sistare If an invariant device name cannot be created, block CPR. Signed-off-by: Steve Sistare Reviewed-by: Zhenzhong Duan Link: https://lore.kernel.org/qemu-devel/1751493538-202042-12-git-send-email-steven.sist...@oracle.com Signed-off-by: Cédric Le Goater --- include/hw/vfio/v

[PULL 15/27] vfio/iommufd: invariant device name

From: Steve Sistare cpr-transfer will use the device name as a key to find the value of the device descriptor in new QEMU. However, if the descriptor number is specified by a command-line fd parameter, then vfio_device_get_name creates a name that includes the fd number. This causes a chicken-an

[PULL 12/27] backends/iommufd: change process ioctl

From: Steve Sistare Define the change process ioctl Signed-off-by: Steve Sistare Reviewed-by: Cédric Le Goater Reviewed-by: Zhenzhong Duan Link: https://lore.kernel.org/qemu-devel/1751493538-202042-7-git-send-email-steven.sist...@oracle.com Signed-off-by: Cédric Le Goater --- include/syste

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