Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Peter Maydell
On Wed, 5 Aug 2020 at 18:00, Richard Henderson wrote: > Older ones like XSCALE are obvious Looking at the XScale manual we could actually implement ARM_FEATURE_XSCALE as (cpu->midr & 0x == 0x6905) [Vendor=intel, arch=ARMv5TE], and ARM_FEATURE_IWMMXT as (cpu->midr & 0xe000 == 0x690

Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Peter Maydell
On Wed, 5 Aug 2020 at 18:00, Richard Henderson wrote: > I've always assumed we'd never get rid of all of them. > > Older ones like XSCALE are obvious, but I don't think there's a clear > indicator > for V{5,6,7,8} either. MIDR.Architecture lets you distinguish v4/v4T/v5/v5T/v5TE/v5TEJ/v6, and th

Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Richard Henderson
On 8/5/20 9:52 AM, Peter Maydell wrote: > On Wed, 5 Aug 2020 at 17:45, Alex Bennée wrote: >> I wouldn't test other feature bits but what stopping us adding: >> >> struct ARMISARegisters { >> uint32_t id_isar0; >> ... >> uint64_t id_aa64dfr1; >> /* >> *

Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Peter Maydell
On Wed, 5 Aug 2020 at 17:45, Alex Bennée wrote: > I wouldn't test other feature bits but what stopping us adding: > > struct ARMISARegisters { > uint32_t id_isar0; > ... > uint64_t id_aa64dfr1; > /* > * The following are synthetic flags for features not

Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Alex Bennée
Richard Henderson writes: > On 8/5/20 4:08 AM, Peter Maydell wrote: >> Mostly recently we've been aiming for QEMU emulation code in >> target/arm to use ID register fields to determine whether a >> feature is present or not (the isar_feature_* functions) rather >> than the old style of defining

Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Richard Henderson
On 8/5/20 4:08 AM, Peter Maydell wrote: > Mostly recently we've been aiming for QEMU emulation code in > target/arm to use ID register fields to determine whether a > feature is present or not (the isar_feature_* functions) rather > than the old style of defining ARM_FEATURE_* flags. This seems to

Re: v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Philippe Mathieu-Daudé
On 8/5/20 1:08 PM, Peter Maydell wrote: > Mostly recently we've been aiming for QEMU emulation code in > target/arm to use ID register fields to determine whether a > feature is present or not (the isar_feature_* functions) rather > than the old style of defining ARM_FEATURE_* flags. This seems to

v8.1M cpu emulation and target-arm feature-identification strategy

2020-08-05 Thread Peter Maydell
Mostly recently we've been aiming for QEMU emulation code in target/arm to use ID register fields to determine whether a feature is present or not (the isar_feature_* functions) rather than the old style of defining ARM_FEATURE_* flags. This seems to be working out well for A-profile. However, for