Re: riscv: AMO exception is incorrect

On 4/21/25 10:58, Eric DeVolder wrote: Hi, I've noticed what I believe to be an error in the RISC-V implementation.  The RISC-V spec[1] states:  Note that load and load-reserved instructions generate load  exceptions, whereas store, storeconditional, and AMO instructions  generate store/AMO

riscv: AMO exception is incorrect

Hi, I've noticed what I believe to be an error in the RISC-V implementation.  The RISC-V spec[1] states:  Note that load and load-reserved instructions generate load  exceptions, whereas store, storeconditional, and AMO instructions  generate store/AMO exceptions. For an AMO operation, a transla