[PULL 2/2] pci: Fix the update of interrupt disable bit in PCI_COMMAND register

From: Guoyi Tu The PCI_COMMAND register is located at offset 4 within the PCI configuration space and occupies 2 bytes. The interrupt disable bit is at the 10th bit, which corresponds to the byte at offset 5 in the PCI configuration space. In our testing environment, the guest driver may directl

Re: pci: Fix the update of interrupt disable bit in PCI_COMMAND register

On Fri, Aug 11, 2023 at 10:46:51PM +0800, Guoyi Tu wrote: > The PCI_COMMAND register is located at offset 4 within > the PCI configuration space and occupies 2 bytes. The > interrupt disable bit is at the 10th bit, which corresponds > to the byte at offset 5 in the PCI configuration space. > > In

pci: Fix the update of interrupt disable bit in PCI_COMMAND register

The PCI_COMMAND register is located at offset 4 within the PCI configuration space and occupies 2 bytes. The interrupt disable bit is at the 10th bit, which corresponds to the byte at offset 5 in the PCI configuration space. In our testing environment, the guest driver may directly updates the by