> > +{
> > +.name = "MyCPU",
> > +.insn_flags = CPU_MIPS1 | INSN_MYCPU,
> > +},
> > ...
> > I just need to simulate it's instruction set in linux user emulation, I
> > didn't include CP0* items in the list. Is this good enough to add a new CPU
> > model?
> Something like that might be ac
On 9/26/19 4:31 PM, Libo Zhou wrote:
>> If you look at the mips_defs[] array in
>> target/mips/translate_init.inc.c, the older ISA implemented is MIPS-II:
>
>> $ git grep .insn_flags target/mips/translate_init.inc.c
>> translate_init.inc.c:75:.insn_flags = CPU_MIPS32,
>> translate_init.inc
> If you look at the mips_defs[] array in
> target/mips/translate_init.inc.c, the older ISA implemented is MIPS-II:
> $ git grep .insn_flags target/mips/translate_init.inc.c
> translate_init.inc.c:75:.insn_flags = CPU_MIPS32,
> translate_init.inc.c:97:.insn_flags = CPU_MIPS32 | ASE
On 9/24/19 3:31 PM, Libo Zhou wrote:
>>> I would start by using the QEMU gdbstub to connect a
>>> MIPS-aware gdb. Then when the SIGILL arrives you can see
>>> what instruction the guest program was trying to execute.
>
>> Just tried it and found something interesting.
>> I connected gdb-multiarch
> > I would start by using the QEMU gdbstub to connect a
> > MIPS-aware gdb. Then when the SIGILL arrives you can see
> > what instruction the guest program was trying to execute.
> Just tried it and found something interesting.
> I connected gdb-multiarch to QEMU gdbstub. gdb-multiarch's architec
On Tue, 24 Sep 2019 at 02:10, Libo Zhou wrote:
>
> > Can you run QEMU with some debugging options:
>
> > qemu-mipsel -d in_asm,exec,cpu,unimp,guest_errors,nochain -D debug.log
> > -singlestep test
>
> > and then put the resulting debug.log somewhere we can get it?
> > (it'll probably be quite larg
> I would start by using the QEMU gdbstub to connect a
> MIPS-aware gdb. Then when the SIGILL arrives you can see
> what instruction the guest program was trying to execute.
Just tried it and found something interesting.
I connected gdb-multiarch to QEMU gdbstub. gdb-multiarch's architecture was s
> I would start by using the QEMU gdbstub to connect a
> MIPS-aware gdb. Then when the SIGILL arrives you can see
> what instruction the guest program was trying to execute.
Just tried it and found something interesting.
I connected gdb-multiarch to QEMU gdbstub. gdb-multiarch's architecture was s
> I would start by using the QEMU gdbstub to connect a
> MIPS-aware gdb. Then when the SIGILL arrives you can see
> what instruction the guest program was trying to execute.
Just tried it and found something interesting.
I connected gdb-multiarch to QEMU gdbstub. gdb-multiarch's architecture was s
> Can you run QEMU with some debugging options:
> qemu-mipsel -d in_asm,exec,cpu,unimp,guest_errors,nochain -D debug.log
> -singlestep test
> and then put the resulting debug.log somewhere we can get it?
> (it'll probably be quite large)
The logging only shows this little information. It seems l
On Mon, 23 Sep 2019 at 17:26, Libo Zhou wrote:
>
> Hi Philippe, Peter,
>
> In target/mips/translate_init.inc.c you can actually see that CPU_MIPS32
> ultimately contains ISA_MIPS1. It's just no CPU model explicitly uses
> ISA_MIPS. But I agree that if my assembly has a removed instruction then i
't think that's a problem though.
Please let me know if you need more information. I appreciate your help.
Thanks,
Libo Zhou
-- Original ----------
From: "Philippe Mathieu-Daud ";;
Send time: Monday, Sep 23, 2019 10:50 PM
To: "Peter Maydell";
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