that is done before I try
to claim there are additional issues here.
Michael
-Original Message-
From: Richard Henderson
Sent: Monday, June 21, 2021 4:30 PM
To: Michael Morrell ; qemu-devel@nongnu.org
Subject: Re: Denormal input handling
On 6/21/21 4:13 PM, Michael Morrell wrote:
> I have
.
Michael
-Original Message-
From: Richard Henderson
Sent: Monday, June 21, 2021 4:30 PM
To: Michael Morrell ; qemu-devel@nongnu.org
Subject: Re: Denormal input handling
On 6/21/21 4:13 PM, Michael Morrell wrote:
> I have another couple of thoughts around input denormal handling.
>
, June 21, 2021 4:30 PM
To: Michael Morrell ; qemu-devel@nongnu.org
Subject: Re: Denormal input handling
On 6/21/21 4:13 PM, Michael Morrell wrote:
> I have another couple of thoughts around input denormal handling.
>
> The first is straightforward. I noticed that the Aarch64 port doesn'
On 6/21/21 4:13 PM, Michael Morrell wrote:
I have another couple of thoughts around input denormal handling.
The first is straightforward. I noticed that the Aarch64 port doesn't report input
denormals (I could not find any code which sets the IDC bit in the FPSR). I found code in
the arm (n
I have another couple of thoughts around input denormal handling.
The first is straightforward. I noticed that the Aarch64 port doesn't report
input denormals (I could not find any code which sets the IDC bit in the FPSR).
I found code in the arm (not aarch64) port that sets other bits like IX
On 5/26/21 2:59 PM, Michael Morrell wrote:
First, I apologize for the duplicate thread. I thought the first attempt
didn't go through.
I agree with Richard that we need an extra flag bit. The current behavior is
not right for SSE on x86 (it looks like x87 might be different still). For
AR
.
Richard, are you willing to make the change or do you want me to try?
Thanks,
Michael
-Original Message-
From: Peter Maydell
Sent: Wednesday, May 26, 2021 1:19 PM
To: Michael Morrell
Cc: qemu-devel@nongnu.org; Richard Henderson
Subject: Re: Denormal input handling
On Wed, 26 May
So, DE should not be set for a denormal input if DAZ is set (it is set only
when DAZ is 0 -- the default "IEEE mode").
It's not my day is it? Clearly the bit that I quoted is wrt to the output
denormal flushing. But my suggested fix is still not wrong -- have two bits
that cover both alterna
On Wed, 26 May 2021 at 20:07, Michael Morrell wrote:
> I see support in QEMU for architectures which have a denormal
> input flag bit and those that have a "flush inputs to zero" control
> bit, but the implementation is not specializable and seems wrong
> for x86 at least.
> For example, in sf_ca
Richard,
How is what I suggested wrong for x86? It matches the spec and actual behavior:
== Start quote ==
10.2.3.4 Denormals-Are-Zeros
Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which
controls the processor’s response
to a SIMD floating-point denormal operand con
On 5/26/21 12:23 PM, Richard Henderson wrote:
On 5/26/21 12:02 PM, Michael Morrell via wrote:
I think the behavior should be for denormal inputs that if
"flush_inputs_to_zero" is true, then set the value to zero (without setting
the "input denormal" flag); and if "flush_inputs_to_zero" is false
On 5/26/21 12:02 PM, Michael Morrell via wrote:
I think the behavior should be for denormal inputs that if "flush_inputs_to_zero" is true, then set the value
to zero (without setting the "input denormal" flag); and if "flush_inputs_to_zero" is false, set
the "input denormal" flag and normalize
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