> -Original Message-
> From: Alistair Francis
> Sent: Wednesday, August 7, 2024 6:59 PM
> To: Alvin Che-Chia Chang(張哲嘉)
> Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org;
> alistair.fran...@wdc.com
> Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra tr
emu-devel@nongnu.org;
> > alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com;
> > dbarb...@ventanamicro.com; zhiwei_...@linux.alibaba.com
> > Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR
> > functions
> >
> > [EXTERN
gmail.com;
> dbarb...@ventanamicro.com; zhiwei_...@linux.alibaba.com
> Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR
> functions
>
> [EXTERNAL MAIL]
>
> On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via
> wrote:
> >
> > According to RISC-V Debug specificatio
On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via wrote:
>
> According to RISC-V Debug specification, the optional textra32 and textra64
> trigger CSRs can be used to configure additional matching conditions for the
> triggers.
>
> This series support to write MHVALUE and MHSELECT fields into textra
