On Sat, Oct 1, 2022 at 11:33 AM Eric Chan wrote:
>
> Hi, qemu
>
> As I know, brom will pass 3 parameters to the next stage bootloader, ex:
> openSBI.
> a0 will pass hartid, a2 will pass fw_dynamic_info start address.
> although a1 doesn't use directly in openSBI.
> a1 read value is determined in
> 抄 送：qemu-riscv
> 主 题：Re: Question about RISC-V brom register a1 set value
>
> Cc'ing the RISC-V specific mailing list.
>
> On 1/10/22 01:48, Eric Chan wrote:
> > Hi, qemu
> >
> > As I know, brom will pass 3 parameters to the next stage bootloader, ex:
&
日(星期一) 20:37
收件人：Eric Chan ; qemu-devel
抄 送：qemu-riscv
主 题：Re: Question about RISC-V brom register a1 set value
Cc'ing the RISC-V specific mailing list.
On 1/10/22 01:48, Eric Chan wrote:
> Hi, qemu
>
> As I know, brom will pass 3 parameters to the next stage bootloader, ex:
> o
Cc'ing the RISC-V specific mailing list.
On 1/10/22 01:48, Eric Chan wrote:
Hi, qemu
As I know, brom will pass 3 parameters to the next stage bootloader, ex:
openSBI.
a0 will pass hartid, a2 will pass fw_dynamic_info start address.
although a1 doesn't use directly in openSBI.
a1 read value is
Hi, qemu
As I know, brom will pass 3 parameters to the next stage bootloader, ex:
openSBI.
a0 will pass hartid, a2 will pass fw_dynamic_info start address.
although a1 doesn't use directly in openSBI.
a1 read value is determined in compile time rather than read from the
original a1 that passes fro
