On Thu, Oct 17, 2024 at 6:41 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this new version we fixed address alignment issues in some command
> queue commands, pointed out by Jason in v9.
>
> No other changes made. Series based on alistair/riscv-to-apply.next.
>
> All patches reviewed.
>
> Chan
Hi,
In this new version we fixed address alignment issues in some command
queue commands, pointed out by Jason in v9.
No other changes made. Series based on alistair/riscv-to-apply.next.
All patches reviewed.
Changes from v9:
- patch 3:
- fixed cmd.dword1 alignment in riscv_iommu_process_cq_t
Hi,
In this new version we fixed the IOVA == GPA MSI early check in patch 3,
in riscv_iommu_spa_fetch(), after discussions with Tomasz and Drew on
v8.
The motivation behind what was being was making the emulation work with
the existing VFIO irqbypass support in the kernel. In the end this was
not
Hi,
We had problems right at the finish line of the pull request due to endianness
problems reported in the Gitlab CI [1]. This triggered discussions in the
middle of the pull request patches [2] that resulted in this new version.
We dealt with the endianness problem that was hitting the Gitlab C
On Wed, Sep 4, 2024 at 6:17 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this new version the only significant code change was made in patch
> 3, where we're no longer modifying the host address with the translated
> address. The remaining of the changes consist in adding more in-code
> docs (
Hi,
In this new version the only significant code change was made in patch
3, where we're no longer modifying the host address with the translated
address. The remaining of the changes consist in adding more in-code
docs (a.k.a comments) on the design choices made in the emulation.
The docs were
Hi,
In this new version the most notable change is how we're dealing with
ICVEC updates. Instead of hardcoding the vectors being used in
riscv-iommu-pci, a new interface was created to allow IOMMU devices to
receive ICVEC updates and act accordingly.
riscv-iommu-pci will receive this notification
Hi,
In this new version changes based on the suggestions made in v4 were
made.
The most notable change, however, is the merge of patches 3 (base IOMMU
emulation and 9 (s-stage and g-stage) from v4 into a single patch. There
were several instances throughout the revisions of this work where a
comm
On Sat, Jul 6, 2024 at 7:26 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Would it make it easier for review if we squash patch 3:
>
> [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
>
> and patch 8:
>
> [PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support
>
> In the s
ster.
Patches missing reviews/acks: 3, 9, 14
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest.
The Linux kernel used for tests can be found here:
https://
4
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest.
The Linux kernel used for tests can be found here:
https://github.com/tjeznach/linux/tree/riscv_iommu_v6-rc3
patch 3. Link for the previous version is [1].
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting
a QEMU
KVM guest, passing through an emulated e1000 network card from the
host
to the guest. I can provide more details (e.g. QEMU command lines) if
required, just l
Thanks,
Daniel
Thanks,
Zhiwei
On 2024/5/24 1:39, Daniel Henrique Barboza wrote:
Hi,
In this new version a lot of changes were made throughout all the code,
most notably on patch 3. Link for the previous version is [1].
* How it was tested *
This series was tested using an emulated QEMU RISC-V
How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a
QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest. I can provide more details (e.g. QEMU command lines) if
required, just let me know. For now this cover-letter is too much o
code,
most notably on patch 3. Link for the previous version is [1].
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest. I can provide more details (e.g. QEMU command
the code,
most notably on patch 3. Link for the previous version is [1].
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest. I can provide more details (e.g. QEMU
e:
> >>>
> >>> Hi,
> >>>
> >>> In this new version a lot of changes were made throughout all the code,
> >>> most notably on patch 3. Link for the previous version is [1].
> >>>
> >>> * How it was tested *
> >
previous version is [1].
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest. I can provide more details (e.g. QEMU command lines) if
required, just let me know. For now this
previous version is [1].
>>
>> * How it was tested *
>>
>> This series was tested using an emulated QEMU RISC-V host booting a QEMU
>> KVM guest, passing through an emulated e1000 network card from the host
>> to the guest. I can provide more details (e.g. QEMU co
On Fri, May 24, 2024 at 3:43 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this new version a lot of changes were made throughout all the code,
> most notably on patch 3. Link for the previous version is [1].
>
> * How it was tested *
>
> This series was tested us
Hi,
In this new version a lot of changes were made throughout all the code,
most notably on patch 3. Link for the previous version is [1].
* How it was tested *
This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card
On 5/10/24 08:14, Frank Chang wrote:
Hi Daniel,
Thanks for the upstream work.
Sorry that it took a while for me to review the patchset.
Please let me know if you need any help from us to update the IOMMU model.
We would like to see it merged for QEMU 9.1.0.
Thanks for the help in the revie
Hi Daniel,
Thanks for the upstream work.
Sorry that it took a while for me to review the patchset.
Please let me know if you need any help from us to update the IOMMU model.
We would like to see it merged for QEMU 9.1.0.
Regards,
Frank Chang
Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:04寫道：
>
Hi,
This is the second version of the work Tomasz sent in July 2023 [1].
I'll be helping Tomasz upstreaming it.
The core emulation code is left unchanged but a few tweaks were made in
v2:
- The most notable difference in this version is that the code was split
in smaller chunks. Patch 03 is s
The RISC-V IOMMU specification is now ratified as-per the RISC-V international
process [1]. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
This series introduces a RISC-V IOMMU device emulation implementation with
On Sun, Jun 25, 2023 at 8:27 AM Peter Samir
wrote:
>
> hello,
> I built RISC-V toolchain and QEMU as follows:
> # Install prerequisites:
> https://github.com/riscv-collab/riscv-gnu-toolchain#prerequisites
> # Install additional prerequisites:
> https://github.com/riscv-collab/riscv-gnu-toolchain
hello,
I built RISC-V toolchain and QEMU as follows:
# Install prerequisites:
https://github.com/riscv-collab/riscv-gnu-toolchain#prerequisites
# Install additional prerequisites:
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1251
git clone https://github.com/riscv-collab/riscv-gnu-too
On Thu, Jun 30, 2022 at 4:27 PM Anup Patel wrote:
>
> On Thu, Jun 30, 2022 at 11:42 AM Anup Patel wrote:
> >
> > This series does fixes and improvements to have nested virtualization
> > on QEMU RISC-V.
> >
> > These patches can also be found in riscv_
On Thu, Jun 30, 2022 at 11:42 AM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v9 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC-V n
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v9 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
On Thu, Jun 16, 2022 at 1:17 PM Anup Patel wrote:
>
> The latest AIA draft v0.3.0 addresses comments from the architecture
> review committee.
> (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
>
> There are primarily two changes:
> 1) Removing various [m|s|vs]seteienum, [m|
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v8 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v7 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
On Sat, Jun 11, 2022 at 6:20 PM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v6 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC-V n
The latest AIA draft v0.3.0 addresses comments from the architecture
review committee.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
There are primarily two changes:
1) Removing various [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum,
and [m|s|vs]clrei;num CSRs
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v6 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v5 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v4 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v3 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
On Thu, May 12, 2022 at 12:47 AM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v2 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC-V n
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v2 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required
This series covers few fixes discovered while trying to detect priv spec
version on QEMU virt machine and QEMU sifive_u machine.
These patches can also be found in riscv_priv_version_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (3):
target/riscv: Don't force update priv sp
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V. The first two patches are fixes whereas the second
two patches make nested virtualization performance better on for
QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v1 branch at:
https
On Sun, Feb 20, 2022 at 6:57 PM Anup Patel wrote:
>
> From: Anup Patel
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> The latest AIA draft speci
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/re
On Thu, Feb 10, 2022 at 8:24 PM Anup Patel wrote:
>
> On Thu, Feb 10, 2022 at 1:58 PM Atish Patra wrote:
> >
> > On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis
> > wrote:
> > >
> > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis
> > > wrote:
> > > >
> > > > On Sat, Feb 5, 2022 at 3:47 AM
On Thu, Feb 10, 2022 at 1:58 PM Atish Patra wrote:
>
> On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis wrote:
> >
> > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis
> > wrote:
> > >
> > > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote:
> > > >
> > > > From: Anup Patel
> > > >
> > > > The a
On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis wrote:
>
> On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote:
> >
> > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote:
> > >
> > > From: Anup Patel
> > >
> > > The advanced interrupt architecture (AIA) extends the per-HART local
> > > interru
On Tue, Feb 8, 2022 at 12:27 PM Alistair Francis wrote:
>
> On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote:
> >
> > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote:
> > >
> > > From: Anup Patel
> > >
> > > The advanced interrupt architecture (AIA) extends the per-HART local
> > > interru
On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote:
>
> On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote:
> >
> > From: Anup Patel
> >
> > The advanced interrupt architecture (AIA) extends the per-HART local
> > interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> > and Adv
On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote:
>
> From: Anup Patel
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> The latest AIA draft specif
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/re
On Fri, Jan 21, 2022 at 2:02 AM Anup Patel wrote:
>
> Hi Alistair,
>
> On Wed, Jan 19, 2022 at 8:56 PM Anup Patel wrote:
> >
> > From: Anup Patel
> >
> > The advanced interrupt architecture (AIA) extends the per-HART local
> > interrupt support. Along with this, it also adds IMSIC (MSI contrllor
Hi Alistair,
On Wed, Jan 19, 2022 at 8:56 PM Anup Patel wrote:
>
> From: Anup Patel
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> The latest A
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/re
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/re
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/re
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/releases/download/0.2
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/releases/download/0.2
Hi Alistair,
On Sat, Oct 23, 2021 at 2:17 PM Anup Patel wrote:
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> The latest AIA draft specification
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/releases/download/0.2
gt; > >
> > > This series:
> > > 1) Replaces SiFive CLINT implementation with RISC-V ACLINT
> > > 2) Refactors RISC-V virt machine FDT generation
> > > 3) Adds optional full ACLINT support in QEMU RISC-V virt machine
> > >
> > > This series can b
) Refactors RISC-V virt machine FDT generation
> > 3) Adds optional full ACLINT support in QEMU RISC-V virt machine
> >
> > This series can be found in the riscv_aclint_v4 branch at:
> > https://github.com/avpatel/qemu.git
> >
> > Changes since v3:
>
n) can be found at:
> https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>
> This series:
> 1) Replaces SiFive CLINT implementation with RISC-V ACLINT
> 2) Refactors RISC-V virt machine FDT generation
> 3) Adds optional full ACLINT support in QEMU RISC-V virt machine
On Sat, Sep 4, 2021 at 7:21 PM Bin Meng wrote:
>
> On Thu, Sep 2, 2021 at 7:26 PM Anup Patel wrote:
> >
> > The advanced interrupt architecture (AIA) extends the per-HART local
> > interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> > and Advanced PLIC (wired interrupt contro
On Thu, Sep 2, 2021 at 7:26 PM Anup Patel wrote:
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> The latest AIA draft specification can be found h
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/releases/download/0.2
This series:
1) Replaces SiFive CLINT implementation with RISC-V ACLINT
2) Refactors RISC-V virt machine FDT generation
3) Adds optional full ACLINT support in QEMU RISC-V virt machine
This series can be found in the riscv_aclint_v4 branch at:
https://github.com/avpatel/qemu.git
Changes since v3
This series:
1) Replaces SiFive CLINT implementation with RISC-V ACLINT
2) Refactors RISC-V virt machine FDT generation
3) Adds optional full ACLINT support in QEMU RISC-V virt machine
This series can be found in the riscv_aclint_v3 branch at:
https://github.com/avpatel/qemu.git
Changes since v2
This series:
1) Replaces SiFive CLINT implementation with RISC-V ACLINT
2) Refactors RISC-V virt machine FDT generation
3) Adds optional full ACLINT support in QEMU RISC-V virt machine
This series can be found in the riscv_aclint_v2 branch at:
https://github.com/avpatel/qemu.git
Changes since v1
On Thu, Nov 7, 2019 at 10:22 PM Palmer Dabbelt wrote:
>
> On Wed, 06 Nov 2019 03:56:29 PST (-0800), Anup Patel wrote:
> > This series adds RTC device to QEMU RISC-V virt machine. We have
> > selected Goldfish RTC device model for this. It's a pretty simple
> > s
On 11/7/19 5:52 PM, Palmer Dabbelt wrote:
On Wed, 06 Nov 2019 03:56:29 PST (-0800), Anup Patel wrote:
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no depen
On Wed, 06 Nov 2019 03:56:29 PST (-0800), Anup Patel wrote:
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish R
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
On Sat, 02 Nov 2019 03:37:42 PDT (-0700), Peter Maydell wrote:
On Tue, 29 Oct 2019 at 13:25, Alistair Francis wrote:
On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
>
> This series adds RTC device to QEMU RISC-V virt machine. We have
> selected Goldfish RTC device model for thi
On Sat, Nov 2, 2019 at 3:37 AM Peter Maydell wrote:
>
> On Tue, 29 Oct 2019 at 13:25, Alistair Francis wrote:
> >
> > On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
> > >
> > > This series adds RTC device to QEMU RISC-V virt machine. We have
> > >
gt; >>
> > >> On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
> > >> >
> > >> > This series adds RTC device to QEMU RISC-V virt machine. We have
> > >> > selected Goldfish RTC device model for this. It's a pretty simple
> &
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
;> >
> >> > This series adds RTC device to QEMU RISC-V virt machine. We have
> >> > selected Goldfish RTC device model for this. It's a pretty simple
> >> > synthetic device with few MMIO registers and no dependency external
> >> > cl
On Tue, 29 Oct 2019 at 13:25, Alistair Francis wrote:
>
> On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
> >
> > This series adds RTC device to QEMU RISC-V virt machine. We have
> > selected Goldfish RTC device model for this. It's a pretty simple
> > synth
On Fri, 01 Nov 2019 08:40:24 PDT (-0700), a...@brainfault.org wrote:
On Tue, Oct 29, 2019 at 6:55 PM Alistair Francis wrote:
On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
>
> This series adds RTC device to QEMU RISC-V virt machine. We have
> selected Goldfish RTC device model
On Tue, Oct 29, 2019 at 6:55 PM Alistair Francis wrote:
>
> On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
> >
> > This series adds RTC device to QEMU RISC-V virt machine. We have
> > selected Goldfish RTC device model for this. It's a pretty simple
>
On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote:
>
> This series adds RTC device to QEMU RISC-V virt machine. We have
> selected Goldfish RTC device model for this. It's a pretty simple
> synthetic device with few MMIO registers and no dependency external
> clock. The driver
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
; Anup Patel
> Subject: Re: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
>
>
> On Tue, Sep 24, 2019 at 08:42:36AM +, Anup Patel wrote:
> > This series adds RTC device to QEMU RISC-V virt machine. We have
> > selected Goldfish RTC device model for this. It&#
On Tue, Sep 24, 2019 at 08:42:36AM +, Anup Patel wrote:
> This series adds RTC device to QEMU RISC-V virt machine. We have
> selected Goldfish RTC device model for this. It's a pretty simple
> synthetic device with few MMIO registers and no dependency external
> cloc
kar ;
> > Bastian Koppelmann ; Atish Patra
> > ; qemu-ri...@nongnu.org; qemu-
> > de...@nongnu.org; Anup Patel
> > Subject: Re: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
> >
> >
> > On Tue, Sep 24, 2019 at 08:42:36AM +, Anup Patel wrote:
&
; Anup Patel
> Subject: Re: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
>
> On Fri, Sep 27, 2019 at 12:05:43PM +, Anup Patel wrote:
> >
> >
> > > -Original Message-
> > > From: Richard W.M. Jones
> > > Sent: Friday, September
i...@nongnu.org; qemu-
> de...@nongnu.org; Anup Patel
> Subject: Re: [PATCH v2 0/2] RTC support for QEMU RISC-V virt machine
>
> Hi Anup,
>
> On 9/24/19 3:11 PM, Anup Patel wrote:
> > This series adds RTC device to QEMU RISC-V virt machine. We have
> > selected Goldfish RTC
Hi Anup,
On 9/24/19 3:11 PM, Anup Patel wrote:
> This series adds RTC device to QEMU RISC-V virt machine. We have
> selected Goldfish RTC device model for this. It's a pretty simple
> synthetic device with few MMIO registers and no dependency external
> clock. The driver fo
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
This series adds RTC device to QEMU RISC-V virt machine. We have
selected Goldfish RTC device model for this. It's a pretty simple
synthetic device with few MMIO registers and no dependency external
clock. The driver for Goldfish RTC is already available in Linux so
we just need to enable
Hi Paolo,
Thanks for the information.
Fred
On 08/23/2017 10:29 PM, Paolo Bonzini wrote:
On 23/08/2017 21:25, KONRAD Frederic wrote:
Hi all,
I found somes slides about RISC-V at the KVM forum 2016.
Seems the upstreaming process should have started in september 2016 but
I didn't see anything.
On 23/08/2017 21:25, KONRAD Frederic wrote:
> Hi all,
>
> I found somes slides about RISC-V at the KVM forum 2016.
>
> Seems the upstreaming process should have started in september 2016 but
> I didn't see anything.
>
> Is that still planed?
We're waiting from the privileged interface specifica
Hi all,
I found somes slides about RISC-V at the KVM forum 2016.
Seems the upstreaming process should have started in september
2016 but I didn't see anything.
Is that still planed?
Thanks,
Fred
Bastian Koppelmann writes:
> On 07/25/2017 06:37 PM, Bruce Hoult wrote:
>> Do you have any good estimates for how much of the execution time is
>> typically spent in instruction decode?
>>
>> RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing
>> something right!
>>
>> (I suspect
> On 27 Jul 2017, at 8:58 AM, kr...@berkeley.edu wrote:
>
>
> Given that one of the goals of RISC-V is extensibility, it would be
> nice if the QEMU port was done in a way to make it easier to extend by
> third parties, including other automated tools. I'm sure that, over
> time, the preprocess
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