On Tue, Jan 2, 2024 at 7:22 PM Nati Rapaport wrote:
>
> Hello,
>
> I’m going to add some custom CSRs (Control & Status Registers) to a new RiscV
> core in qemu.
>
> Could you please help me understanding if there is any method to do it?
Have a look at decode_opc() in target/riscv/translate.c.
W
Hello,
I'm going to add some custom CSRs (Control & Status Registers) to a new RiscV
core in qemu.
Could you please help me understanding if there is any method to do it?
Should I do it in /target/riscv/cpu_bits.h where all CSRs are defined (and
other files, where all standard CSRs implementatio
