Re: [RFC v5 0/4] Add QEMU model for ASPEED OTP memory and integrate with SoCs

2025-06-23 Thread Cédric Le Goater
Hello Kane, On 6/23/25 05:23, Kane Chen wrote: Hi Cédric, Sure, I will submit a follow-up patch that includes the following changes: 1. Introduce a new OTP memory device model, which provides in-memory storage and implements basic MMIO read/write via address space. 2. Initialize the OTP memor

RE: [RFC v5 0/4] Add QEMU model for ASPEED OTP memory and integrate with SoCs

2025-06-22 Thread Kane Chen
t: Friday, June 20, 2025 1:44 PM > To: Kane Chen ; Peter Maydell > ; Steven Lee ; Troy > Lee ; Jamin Lin ; Andrew > Jeffery ; Joel Stanley ; > open list:ASPEED BMCs ; open list:All patches CC > here > Cc: Troy Lee > Subject: Re: [RFC v5 0/4] Add QEMU model for ASPEED OTP

Re: [RFC v5 0/4] Add QEMU model for ASPEED OTP memory and integrate with SoCs

2025-06-19 Thread Cédric Le Goater
Hello Kane, On 6/19/25 08:41, Kane Chen wrote: From: Kane-Chen-AS This patch series introduces a QEMU model for the ASPEED OTP (One-Time Programmable) memory, along with its integration into the Secure Boot Controller (SBC) and supported SoCs (AST2600, AST1030). The OTP model emulates a simpl

[RFC v5 0/4] Add QEMU model for ASPEED OTP memory and integrate with SoCs

2025-06-18 Thread Kane Chen via
From: Kane-Chen-AS This patch series introduces a QEMU model for the ASPEED OTP (One-Time Programmable) memory, along with its integration into the Secure Boot Controller (SBC) and supported SoCs (AST2600, AST1030). The OTP model emulates a simple fuse array used for secure boot or device config