On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> +void smmuv3_accel_init_regs(SMMUv3State *s)
> +{
> +SMMUv3AccelState *s_accel = s->s_accel;
> +SMMUv3AccelDevice *accel_dev;
> +uint32_t data_type;
> +uint32_t val;
> +int ret;
> +
> +if (s_accel->info.idr[
On Wed, Jul 16, 2025 at 03:42:39PM -0300, Jason Gunthorpe wrote:
> On Wed, Jul 16, 2025 at 11:09:45AM -0700, Nicolin Chen wrote:
> > OK. I see your point. That will leads to a very long list of
> > parameters.
>
> I would have some useful prebaked ones. Realistically there are not
> that many comb
On Wed, Jul 16, 2025 at 11:09:45AM -0700, Nicolin Chen wrote:
> OK. I see your point. That will leads to a very long list of
> parameters.
I would have some useful prebaked ones. Realistically there are not
that many combinations of HW capabilities that are
interesting/exist.
> So, a vSMMU model
On Wed, Jul 16, 2025 at 10:26:21AM +, Shameerali Kolothum Thodi wrote:
> > On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> > My vSMMU didn't work until I added entries like SIDSIZE, SSIDSIZE,
> > TERM_MODEL, STALL_MODEL, and RIL.
>
> How come your vSMMU not working? Or you
On Wed, Jul 16, 2025 at 02:45:06PM -0300, Jason Gunthorpe wrote:
> On Wed, Jul 16, 2025 at 10:35:25AM -0700, Nicolin Chen wrote:
> > On Wed, Jul 16, 2025 at 08:51:23AM -0300, Jason Gunthorpe wrote:
> > > On Tue, Jul 15, 2025 at 07:57:57PM -0700, Nicolin Chen wrote:
> > > > > +val = FIELD_EX32(s
On Wed, Jul 16, 2025 at 10:35:25AM -0700, Nicolin Chen wrote:
> On Wed, Jul 16, 2025 at 08:51:23AM -0300, Jason Gunthorpe wrote:
> > On Tue, Jul 15, 2025 at 07:57:57PM -0700, Nicolin Chen wrote:
> > > > +val = FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN4K);
> > > > +if (val < FIELD_EX32(s->
On Wed, Jul 16, 2025 at 08:51:23AM -0300, Jason Gunthorpe wrote:
> On Tue, Jul 15, 2025 at 07:57:57PM -0700, Nicolin Chen wrote:
> > > +val = FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN4K);
> > > +if (val < FIELD_EX32(s->idr[5], IDR5, GRAN4K)) {
> > > +s->idr[5] = FIELD_DP32(s->idr[
On Tue, Jul 15, 2025 at 07:57:57PM -0700, Nicolin Chen wrote:
> > +val = FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN4K);
> > +if (val < FIELD_EX32(s->idr[5], IDR5, GRAN4K)) {
> > +s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, val);
> > +}
> > +val = FIELD_EX32(s_accel->inf
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> mo...@nvidia.com; smost...@google.com; Linuxarm
> ; Wangzhou (B) ;
> jiangkunkun ; Jonathan Cameron
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> Subject: Re: [RFC PATCH v3 14/15] Read and validate host SM
On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SI
On Mon, 14 Jul 2025 16:59:40 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SIDSIZE
On Mon, Jul 14, 2025 at 01:04:02PM -0700, Nicolin Chen wrote:
> On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> > From: Nicolin Chen
> >
> > Not all fields in the SMMU IDR registers are meaningful for userspace.
> > Only the following fields can be used:
> >
> > - IDR0: ST_
On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SI
From: Nicolin Chen
Not all fields in the SMMU IDR registers are meaningful for userspace.
Only the following fields can be used:
- IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
- IDR1: SIDSIZE, SSIDSIZE
- IDR3: BBML, RIL
- IDR5: VAX, GRAN64K, GRAN16K, GRAN4K
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