Re: [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode

2021-06-27 Thread Frank Chang
LIU Zhiwei 於 2021年4月9日 週五 下午3:54寫道: > Decode CLIC interrupt information from exccode, includes interrupt > priviledge mode, interrupt level, and irq number. > > Then update CSRs xcause, xstatus, xepc, xintstatus and jump to > correct PC according to the CLIC specification. > > Signed-off-by: LIU

[RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode

2021-04-09 Thread LIU Zhiwei
Decode CLIC interrupt information from exccode, includes interrupt priviledge mode, interrupt level, and irq number. Then update CSRs xcause, xstatus, xepc, xintstatus and jump to correct PC according to the CLIC specification. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 1 + ta