On Tue, May 11, 2021 at 2:01 PM Wang Junqiang wrote:
>
>
>
> On 2021/5/11 上午11:43, Alistair Francis wrote:
> > On Tue, May 11, 2021 at 1:14 PM Wang Junqiang
> > wrote:
> >>
> >>
> >>
> >> On 2021/5/10 上午10:17, Alistair Francis wrote:
> >>>C isOn Fri, May 7, 2021 at 11:25 PM wangjunqiang
> >>
On 2021/5/11 上午11:43, Alistair Francis wrote:
On Tue, May 11, 2021 at 1:14 PM Wang Junqiang wrote:
On 2021/5/10 上午10:17, Alistair Francis wrote:
C isOn Fri, May 7, 2021 at 11:25 PM wangjunqiang
wrote:
This patch adds Nuclei CSR support for ECLIC and update the
related interrupt han
On Tue, May 11, 2021 at 1:14 PM Wang Junqiang wrote:
>
>
>
> On 2021/5/10 上午10:17, Alistair Francis wrote:
> > C isOn Fri, May 7, 2021 at 11:25 PM wangjunqiang
> > wrote:
> >>
> >> This patch adds Nuclei CSR support for ECLIC and update the
> >> related interrupt handling.
> >>
> >> https://doc
On 2021/5/10 上午10:17, Alistair Francis wrote:
C isOn Fri, May 7, 2021 at 11:25 PM wangjunqiang
wrote:
This patch adds Nuclei CSR support for ECLIC and update the
related interrupt handling.
https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html
Hello,
Thanks for the patches!
This pa
C isOn Fri, May 7, 2021 at 11:25 PM wangjunqiang
wrote:
>
> This patch adds Nuclei CSR support for ECLIC and update the
> related interrupt handling.
>
> https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html
Hello,
Thanks for the patches!
This patch is very long and you will need to split it
This patch adds Nuclei CSR support for ECLIC and update the
related interrupt handling.
https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html
---
target/riscv/cpu.c | 25 +-
target/riscv/cpu.h | 42 ++-
target/riscv/cpu_bits.h | 37 ++