LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道：
> The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table,
> aligned on a 64-byte or greater power-of-two boundary.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr
The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table,
aligned on a 64-byte or greater power-of-two boundary.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 2 ++
target/riscv/csr.c | 28
3 files ch
