Re: [REPOST PATCH v3 0/5] Support x2APIC mode with TCG accelerator

On 4/11/23 21:24, Bui Quang Minh wrote: [Reposting due to broken threading in previous post] Hi everyone, This series implements x2APIC mode in userspace local APIC and the RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu and AMD iommu are adjusted to support x2APIC int

Re: [REPOST PATCH v3 0/5] Support x2APIC mode with TCG accelerator

On 4/21/23 14:57, Michael S. Tsirkin wrote: On Tue, Apr 11, 2023 at 09:24:35PM +0700, Bui Quang Minh wrote: [Reposting due to broken threading in previous post] Hi everyone, This series implements x2APIC mode in userspace local APIC and the RDMSR/WRMSR helper to access x2APIC registers in x2AP

Re: [REPOST PATCH v3 0/5] Support x2APIC mode with TCG accelerator

On Tue, Apr 11, 2023 at 09:24:35PM +0700, Bui Quang Minh wrote: > [Reposting due to broken threading in previous post] > > Hi everyone, > > This series implements x2APIC mode in userspace local APIC and the > RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu > and AMD iomm

[REPOST PATCH v3 0/5] Support x2APIC mode with TCG accelerator

[Reposting due to broken threading in previous post] Hi everyone, This series implements x2APIC mode in userspace local APIC and the RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu and AMD iommu are adjusted to support x2APIC interrupt remapping. With this series, we can