I can confirm that native gdb64 talking to x86 Qemu gets incorrect double
float registers values, 32-bit looks fine.
My understanding is that gdb considers sparc64 to have 48 "registers". The
first 32 are the same as sparc32, the last 16 (named f32, f34 ... f62) are
double precision registers. gdb then overlays this with d and q regs, but
we
don't need to care about that.
Quoting the V9 manual:
The FPU contai
I'm currently reqriting bits of the qemu gdb stub to take advantage of new GDB
target description mechanisms, and have come accross what looks like a bug in
the sparc64 code.
My understanding is that gdb considers sparc64 to have 48 "registers". The
first 32 are the same as sparc32, the last 1
