On Sat, Apr 21, 2012 at 3:06 AM, Blue Swirl wrote:
> On Fri, Apr 20, 2012 at 04:25, Xin Tong wrote:
>> On Thu, Apr 19, 2012 at 6:56 PM, Xin Tong wrote:
>>> On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
> but should not the address be
On Fri, Apr 20, 2012 at 04:25, Xin Tong wrote:
> On Thu, Apr 19, 2012 at 6:56 PM, Xin Tong wrote:
>> On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
>>> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
but should not the address be within 1 - 4G-1 even with PAE. is not
the PAE just u
On Thu, Apr 19, 2012 at 22:56, Xin Tong wrote:
> On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
>> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
>>> but should not the address be within 1 - 4G-1 even with PAE. is not
>>> the PAE just using 64bits addresses as supposed to 32 bit ? what does
On Thu, Apr 19, 2012 at 6:56 PM, Xin Tong wrote:
> On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
>> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
>>> but should not the address be within 1 - 4G-1 even with PAE. is not
>>> the PAE just using 64bits addresses as supposed to 32 bit ? what doe
On Thu, Apr 19, 2012 at 1:03 PM, Blue Swirl wrote:
> On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
>> but should not the address be within 1 - 4G-1 even with PAE. is not
>> the PAE just using 64bits addresses as supposed to 32 bit ? what does
>> the physical address bigger than 4G mean ? is not
On Thu, Apr 19, 2012 at 01:55, Xin Tong wrote:
> but should not the address be within 1 - 4G-1 even with PAE. is not
> the PAE just using 64bits addresses as supposed to 32 bit ? what does
> the physical address bigger than 4G mean ? is not the physical
> address starting from 0 from the prospect
but should not the address be within 1 - 4G-1 even with PAE. is not
the PAE just using 64bits addresses as supposed to 32 bit ? what does
the physical address bigger than 4G mean ? is not the physical
address starting from 0 from the prospective of the processor ?
Xin
On Wed, Apr 18, 2012 at 4:
On Wed, Apr 18, 2012 at 01:28, Xin Tong wrote:
> I am reading how qemu refill TLB working.
>
> target-i386/helper.c
>
> pte = pte & env->a20_mask;
>
> /* Even if 4MB pages, we map only one 4KB page in the cache to
> avoid filling it too fast */
> page_offset = (addr & TARGET_PAGE_MA
I am reading how qemu refill TLB working.
target-i386/helper.c
pte = pte & env->a20_mask;
/* Even if 4MB pages, we map only one 4KB page in the cache to
avoid filling it too fast */
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
paddr = (pte & TARGET_PAGE_MASK)
