> Confused.
> You have one VF accessing BAR of another VF?
> Why?
The VFs are scheduled and the board have only one microcontroller responsible
to give the read results for some memory mapped registers.
So it could respond the value of the active VF when a bar of an inactive VF is
read.
I handed
On Tue, Jun 04, 2013 at 05:50:30PM +0200, Benoît Canet wrote:
>
> Hello,
>
> More informations on how the hardware works.
>
> -Each VF will have its own memory and MMR, etc.
> That means the resources are not shared.
>
> -Each VF will have its own bus number, function number and device number.
On Tue, 2013-06-04 at 17:50 +0200, Benoît Canet wrote:
> Hello,
>
> More informations on how the hardware works.
>
> -Each VF will have its own memory and MMR, etc.
> That means the resources are not shared.
I'm still not clear on MMR, what is that? Memory Mapped Registers (ie.
registers access
Hello,
More informations on how the hardware works.
-Each VF will have its own memory and MMR, etc.
That means the resources are not shared.
-Each VF will have its own bus number, function number and device number.
That means request ID is separated for each VF.
There is also VF save/restore a
On Mon, 2013-06-03 at 14:34 -0400, Don Dutile wrote:
> On 06/03/2013 02:02 PM, Alex Williamson wrote:
> > On Mon, 2013-06-03 at 18:33 +0200, Benoît Canet wrote:
> >> Hello,
> >>
> >> I plan to write a PF driver for an SR-IOV card and make the VFs work with
> >> QEMU's
> >> VFIO passthrough so I am
On 06/03/2013 02:02 PM, Alex Williamson wrote:
On Mon, 2013-06-03 at 18:33 +0200, Benoît Canet wrote:
Hello,
I plan to write a PF driver for an SR-IOV card and make the VFs work with QEMU's
VFIO passthrough so I am asking the following design question before trying to
write and push code.
Afte
On Mon, 2013-06-03 at 18:33 +0200, Benoît Canet wrote:
> Hello,
>
> I plan to write a PF driver for an SR-IOV card and make the VFs work with
> QEMU's
> VFIO passthrough so I am asking the following design question before trying to
> write and push code.
>
> After SR-IOV being enabled on this ha
Hello,
I plan to write a PF driver for an SR-IOV card and make the VFs work with QEMU's
VFIO passthrough so I am asking the following design question before trying to
write and push code.
After SR-IOV being enabled on this hardware only one VF function can be active
at a given time.
The PF host
