On Sun, Jun 25, 2017 at 15:16:46 +0300, Lluís Vilanova wrote:
> Lluís Vilanova writes:
>
> > Jayanto Minocha writes:
> >> Lluis,
> >> My modifications were almost the same as those done by Emilio. There were
> >> no memory trace events in the trace file.
>
> > I'll take a look at it after I finis
On 26 June 2017 at 13:04, Lluís Vilanova wrote:
> Peter Maydell writes:
>
>> On 26 June 2017 at 10:26, Lluís Vilanova wrote:
>>> There's two places where memory access tracing is triggered:
>>>
>>> * tcg_gen_qemu_ld/st_...
>>> * ld/st templates (both softmmu and user)
>>>
>>> AFAIK, helpers use t
Peter Maydell writes:
> On 26 June 2017 at 10:26, Lluís Vilanova wrote:
>> There's two places where memory access tracing is triggered:
>>
>> * tcg_gen_qemu_ld/st_...
>> * ld/st templates (both softmmu and user)
>>
>> AFAIK, helpers use the ld/st templates to access guest memory.
> Mostly, but
On 26 June 2017 at 10:26, Lluís Vilanova wrote:
> There's two places where memory access tracing is triggered:
>
> * tcg_gen_qemu_ld/st_...
> * ld/st templates (both softmmu and user)
>
> AFAIK, helpers use the ld/st templates to access guest memory.
Mostly, but there are one or two special cases
Alex Bennée writes:
> Lluís Vilanova writes:
>> Alex Bennée writes:
>>
>>> Peter Maydell writes:
>>
On 20 June 2017 at 12:02, Lluís Vilanova wrote:
> Jayanto Minocha writes:
>> But that is only used to instrument the cpu_ld/cpu_st macros, which is
>> only
>> called in t
Lluís Vilanova writes:
> Alex Bennée writes:
>
>> Peter Maydell writes:
>
>>> On 20 June 2017 at 12:02, Lluís Vilanova wrote:
Jayanto Minocha writes:
> But that is only used to instrument the cpu_ld/cpu_st macros, which is
> only
> called in the case of a tlb miss.
>
Alex Bennée writes:
> Peter Maydell writes:
>> On 20 June 2017 at 12:02, Lluís Vilanova wrote:
>>> Jayanto Minocha writes:
But that is only used to instrument the cpu_ld/cpu_st macros, which is only
called in the case of a tlb miss.
>>>
I've been going over the archives, and it
Lluís Vilanova writes:
> Jayanto Minocha writes:
>> Lluis,
>> My modifications were almost the same as those done by Emilio. There were
>> no memory trace events in the trace file.
> I'll take a look at it after I finish revamping the generic translation loop
> series (hopefully today).
I just s
Jayanto Minocha writes:
> Lluis,
> My modifications were almost the same as those done by Emilio. There were
> no memory trace events in the trace file.
I'll take a look at it after I finish revamping the generic translation loop
series (hopefully today).
Thanks,
Lluis
> -J
> On Tue, Jun 20
Peter Maydell writes:
> On 20 June 2017 at 12:02, Lluís Vilanova wrote:
>> Jayanto Minocha writes:
>>> But that is only used to instrument the cpu_ld/cpu_st macros, which is only
>>> called in the case of a tlb miss.
>>
>>> I've been going over the archives, and it looks like I need to instrume
Lluis,
My modifications were almost the same as those done by Emilio. There were
no memory trace events in the trace file.
-J
On Tue, Jun 20, 2017 at 10:20 AM, Emilio G. Cota wrote:
> On Tue, Jun 20, 2017 at 14:02:02 +0300, Lluís Vilanova wrote:
> > Jayanto Minocha writes:
> >
> > > Hi,
> > >
On Tue, Jun 20, 2017 at 14:02:02 +0300, Lluís Vilanova wrote:
> Jayanto Minocha writes:
>
> > Hi,
> > I think there have been a few threads on the mailing list regarding tracing
> > guest virtual addresses for load and store instructions, but I have been
> > unable to get it to work. I am trying t
On 20 June 2017 at 12:02, Lluís Vilanova wrote:
> Jayanto Minocha writes:
>> But that is only used to instrument the cpu_ld/cpu_st macros, which is only
>> called in the case of a tlb miss.
>
>> I've been going over the archives, and it looks like I need to instrument
>> tcg_out_tlb_load. Am I on
Jayanto Minocha writes:
> Hi,
> I think there have been a few threads on the mailing list regarding tracing
> guest virtual addresses for load and store instructions, but I have been
> unable to get it to work. I am trying this for an AArch64 machine, and am
> using the softmmu.
> The tracing inf
Hi,
I think there have been a few threads on the mailing list regarding tracing
guest virtual addresses for load and store instructions, but I have been
unable to get it to work. I am trying this for an AArch64 machine, and am
using the softmmu.
The tracing infrastructure provides the following e
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