On Tue, Mar 22, 2011 at 11:07:03PM +0900, Isaku Yamahata wrote:
> On Tue, Mar 22, 2011 at 03:40:16PM +0200, Michael S. Tsirkin wrote:
> > On Tue, Mar 22, 2011 at 09:50:37AM +0900, Isaku Yamahata wrote:
> > > On Mon, Mar 21, 2011 at 04:10:22PM +0200, Michael S. Tsirkin wrote:
> > > > > @@ -37,8 +37,
On Tue, Mar 22, 2011 at 03:40:16PM +0200, Michael S. Tsirkin wrote:
> On Tue, Mar 22, 2011 at 09:50:37AM +0900, Isaku Yamahata wrote:
> > On Mon, Mar 21, 2011 at 04:10:22PM +0200, Michael S. Tsirkin wrote:
> > > > @@ -37,8 +37,27 @@
> > > >
> > > > typedef PCIHostState I440FXState;
> > > >
> >
On Tue, Mar 22, 2011 at 09:50:37AM +0900, Isaku Yamahata wrote:
> On Mon, Mar 21, 2011 at 04:10:22PM +0200, Michael S. Tsirkin wrote:
> > > @@ -37,8 +37,27 @@
> > >
> > > typedef PCIHostState I440FXState;
> > >
> > > +#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
> > > +#define PIIX_
On Mon, Mar 21, 2011 at 04:10:22PM +0200, Michael S. Tsirkin wrote:
> > @@ -37,8 +37,27 @@
> >
> > typedef PCIHostState I440FXState;
> >
> > +#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
> > +#define PIIX_NUM_PIRQS 4ULL/* PIRQ[A-D] */
>
> I've changed this to
> ((uint6
On Sat, Mar 19, 2011 at 10:24:52PM +0900, Isaku Yamahata wrote:
> optimize irq routing in piix_pic.c which has been a TODO.
> So far piix3 tracks each pirq level and checks whether a given pic pins is
> asserted by seeing if each pirq is mapped into the pic pin.
> This is independent on irq routing
On Mon, Mar 21, 2011 at 09:56:56PM +0900, Isaku Yamahata wrote:
> On Mon, Mar 21, 2011 at 02:31:11PM +0200, Michael S. Tsirkin wrote:
> > On Mon, Mar 21, 2011 at 09:10:32PM +0900, Isaku Yamahata wrote:
> > > On Mon, Mar 21, 2011 at 01:37:07PM +0200, Michael S. Tsirkin wrote:
> > > > > +static int p
On Mon, Mar 21, 2011 at 02:31:11PM +0200, Michael S. Tsirkin wrote:
> On Mon, Mar 21, 2011 at 09:10:32PM +0900, Isaku Yamahata wrote:
> > On Mon, Mar 21, 2011 at 01:37:07PM +0200, Michael S. Tsirkin wrote:
> > > > +static int piix3_post_load(void *opaque, int version_id)
> > > > +{
> > > > +PII
On Mon, Mar 21, 2011 at 09:10:32PM +0900, Isaku Yamahata wrote:
> On Mon, Mar 21, 2011 at 01:37:07PM +0200, Michael S. Tsirkin wrote:
> > > +static int piix3_post_load(void *opaque, int version_id)
> > > +{
> > > +PIIX3State *piix3 = opaque;
> > > +piix3_update_irq_levels(piix3);
> >
> > C
On Mon, Mar 21, 2011 at 01:37:07PM +0200, Michael S. Tsirkin wrote:
> > +/* irq routing is changed. so rebuild bitmap */
> > +static void piix3_update_irq_levels(PIIX3State *piix3)
> > +{
> > +int pirq;
> > +
> > +piix3->pic_levels = 0;
> > +for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++)
On Mon, Mar 21, 2011 at 01:37:07PM +0200, Michael S. Tsirkin wrote:
> > +static int piix3_post_load(void *opaque, int version_id)
> > +{
> > +PIIX3State *piix3 = opaque;
> > +piix3_update_irq_levels(piix3);
>
> Couldn't figure out why would we not want to
> propagate the interrupts here.
>
On Sat, Mar 19, 2011 at 10:24:52PM +0900, Isaku Yamahata wrote:
> optimize irq routing in piix_pic.c which has been a TODO.
> So far piix3 tracks each pirq level and checks whether a given pic pins is
> asserted by seeing if each pirq is mapped into the pic pin.
> This is independent on irq routing
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