On 16 May 2013 13:15, François Legal wrote:
> Did anybody pointed out that there may be problems with Qemu decoding these
> MRS/MSR banked registers ?
> In my code, I do several
> mrs %r0, sp_usr
> mrs %r0, lr_usr
>
> from SVC mode or IRQ mode, and the result I get is CPSR in r0
>
> I took
Hello,
Did anybody pointed out that there may be problems with Qemu decoding these
MRS/MSR banked registers ?
In my code, I do several
mrs %r0, sp_usr
mrs %r0, lr_usr
from SVC mode or IRQ mode, and the result I get is CPSR in r0
I took a look in Qemu -> translate.c and op_helper.c, an
