Hi,
What part of the QEMU source code generates translation blocks for mips user
emulation?
Thanks,
Ralf Baechle wrote:
> On Mon, Oct 15, 2007 at 04:05:14PM +0100, Thiemo Seufer wrote:
>
> > I found Qemu/MIPS locks up in the emulated kernel's calibrate_delay
> > function. Switching the kernel option off works around the problem.
>
> I still haven't patched up the issue which was causing the pro
On Mon, Oct 15, 2007 at 04:05:14PM +0100, Thiemo Seufer wrote:
> I found Qemu/MIPS locks up in the emulated kernel's calibrate_delay
> function. Switching the kernel option off works around the problem.
I still haven't patched up the issue which was causing the problem for
Aurel. Is the slow exe
Aurelien Jarno wrote:
> Hi,
>
> As announced by Ralf Baechle, dyntick is now available on MIPS. I gave a
> try on QEMU/MIPS, and unfortunately it doesn't work correctly.
>
> In some cases the kernel schedules an event very near in the future,
> which means the timer is scheduled a few cycles onl
Paul Brook wrote:
There seem to have specific problems when using dynticks in Qemu. What I
can see is that it makes the PowerPC emulation quite unusable, at least
on my PC, which is an amd64 (with a fix CPU frequency), no matter if I
run 32 or 64 bits mode.
I'd expect to see the same probl
> There seem to have specific problems when using dynticks in Qemu. What I
> can see is that it makes the PowerPC emulation quite unusable, at least
> on my PC, which is an amd64 (with a fix CPU frequency), no matter if I
> run 32 or 64 bits mode.
I'd expect to see the same problems running a non-
On Thu, Oct 04, 2007 at 03:59:42AM +0200, J. Mayer wrote:
> > As announced by Ralf Baechle, dyntick is now available on MIPS. I gave a
> > try on QEMU/MIPS, and unfortunately it doesn't work correctly.
Aurelien is talking about a kernel option...
> I tried to disactivate dynticks, just commenting
On Tue, 2007-10-02 at 22:06 +0200, Aurelien Jarno wrote:
> Hi,
Hi,
> As announced by Ralf Baechle, dyntick is now available on MIPS. I gave a
> try on QEMU/MIPS, and unfortunately it doesn't work correctly.
>
> In some cases the kernel schedules an event very near in the future,
> which means t
On Tue, Oct 02, 2007 at 10:57:24PM +0200, Aurelien Jarno wrote:
> From: Aurelien Jarno <[EMAIL PROTECTED]>
> Date: Tue, 02 Oct 2007 22:57:24 +0200
> To: Alan Cox <[EMAIL PROTECTED]>
> CC: qemu-devel@nongnu.org, [EMAIL PROTECTED]
> Subject: Re: [Qemu-devel] QEMU/MIPS &
> Well on real hardware, the instruction rate and the timer are linked:
> the timer run at half the speed of the CPU. As the corresponding
> assembly code is very small, only uses registers and is run in kernel
> mode, you know for sure that 48 cycles is more than enough.
What happens on NMI or if
Alan Cox a écrit :
>> Well on real hardware, the instruction rate and the timer are linked:
>> the timer run at half the speed of the CPU. As the corresponding
>> assembly code is very small, only uses registers and is run in kernel
>> mode, you know for sure that 48 cycles is more than enough.
>
Avi Kivity a écrit :
> Aurelien Jarno wrote:
>> Hi,
>>
>> As announced by Ralf Baechle, dyntick is now available on MIPS. I gave a
>> try on QEMU/MIPS, and unfortunately it doesn't work correctly.
>>
>> In some cases the kernel schedules an event very near in the future,
>> which means the timer i
Aurelien Jarno wrote:
Hi,
As announced by Ralf Baechle, dyntick is now available on MIPS. I gave a
try on QEMU/MIPS, and unfortunately it doesn't work correctly.
In some cases the kernel schedules an event very near in the future,
which means the timer is scheduled a few cycles only from its c
Hi,
As announced by Ralf Baechle, dyntick is now available on MIPS. I gave a
try on QEMU/MIPS, and unfortunately it doesn't work correctly.
In some cases the kernel schedules an event very near in the future,
which means the timer is scheduled a few cycles only from its current
value. Unfortunat
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/08/14 23:39:33
Modified files:
. : mips-dis.c
Log message:
MIPS disassembler update.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/mips-dis.c?cvsroot=qemu&r1=1.5&r2=1.6
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/05/28 13:40:10
Modified files:
. : mips-dis.c
Log message:
MIPS disassembler update.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/mips-dis.c?cvsroot=qemu&r1=1.4&r2=1.5
Hi,
I think emulation of stat() on qemu-mips (big-endian) hosted on x86
is broken. Or more generally, probably either-endian mips on the
opposite-endian host.
In linux-user/syscall.c around line 2892 in the 0.8.2 release, it uses
tswapl() for ppc, and tswap16() for all other targets. But targ
CVSROOT:/sources/qemu
Module name:qemu
Branch:
Changes by: Fabrice Bellard <[EMAIL PROTECTED]> 06/05/22 22:05:04
Modified files:
. : mips-dis.c
Log message:
dump all mips insn (Thiemo Seufer)
CVSWeb URLs:
http://cvs.savannah.gnu.org/view
CVSROOT:/cvsroot/qemu
Module name:qemu
Branch:
Changes by: Fabrice Bellard <[EMAIL PROTECTED]> 05/07/02 14:45:34
Added files:
. : mips-dis.c
Log message:
MIPS disas support
CVSWeb URLs:
http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/m
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