On 11 November 2011 13:44, Cachet Bertrand wrote:
> In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code
> to update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY
> bit ) when writing to the BYTE_TEST register.
As Andreas says, if you can submit your pa
Hi,
Am 11.11.2011 14:44, schrieb Cachet Bertrand:
> Patch is contained in the following commit :
> https://bitbucket.org/bca/qemu-linaro/changeset/0aa1f76e5141
>
> I have sent this patch to qemu-linaro but Peter Maydell (pm215 on #qemu
> IRC channel) told me to send it here because it is against
Hello,
In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code to
update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY bit )
when writing to the BYTE_TEST register.
Writing to PM_CTRL was not permitted before this modification => raise an
harware error
