+cc Richard
On Mon, Jul 2, 2018, 3:30 AM Davidson Francis
wrote:
> Hello,
>
> Thanks for working on this, your tree works fine here and the issue
> seems to be fixed, I have nothing to complain about.
>
Great news.
-Stafford
Regards,
> Davidson Francis.
>
> On 01-07-2018 05:18, Stafford Ho
Hello,
Thanks for working on this, your tree works fine here and the issue
seems to be fixed, I have nothing to complain about.
Regards,
Davidson Francis.
On 01-07-2018 05:18, Stafford Horne wrote:
Hello,
We have been working on a few patches to fixed QEMU for OpenRISC and I
included the chan
Hello,
We have been working on a few patches to fixed QEMU for OpenRISC and I
included the change for picmr writes, richard added some changes to
SPR writes which might help with the masking/umasking work more
reliably.
If you want to try them out could you check:
https://github.com/stffrdhrn/
Thank you for quick reply,
Yes, I've tried, after that, the register works as expected, but even so, if I
enable the interrupts right after, I still receive interrupts from the same IRQ,
but maybe there is something wrong with my code.
Regards,
Davidson Francis.
2018-05-19 23:54 GMT-03:00 Staffo
On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote:
> Hello Stafford,
>
> I'm currently using or1k as a target CPU in an operating system that
> I'm working.
> It happens that I'm having some issues regarding the PICMR register: I realize
> that in the latest Qemu version (2.12) when
