On 30/03/2017 21:30, Gabriele Galeotti wrote:
>
> Hi all.
> According to "GR712RC Dual-Core LEON3FT SPARC V8 Processor User’s Manual",
> "11.3 Registers", pg 87-88, Table 55 Timer control register, the IP
> "interrupt pending"
> bit:
>
> Interrupt Pending (IP): The core sets this bit to ‘1’ when
Hi all.
According to "GR712RC Dual-Core LEON3FT SPARC V8 Processor User’s Manual",
"11.3 Registers", pg 87-88, Table 55 Timer control register, the IP
"interrupt pending"
bit:
Interrupt Pending (IP): The core sets this bit to ‘1’ when an interrupt
is signalled. This bit remains ‘1’
until cle
