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Hi Thierry,
Am 17.07.2012 17:46, schrieb Thierry Reding:
> I've been toying around with adding NVIDIA Tegra support to QEMU.
> While adding SMP support I came across a problem: on Tegra, the
> secondary CPU is kept in reset by the clock-and-reset cont
Hi,
I've been toying around with adding NVIDIA Tegra support to QEMU. While
adding SMP support I came across a problem: on Tegra, the secondary CPU
is kept in reset by the clock-and-reset controller (CRC). When bringing
up the secondary CPU, the OS writes a given register in the CRC to
release the
Hi,
I've been toying around with adding NVIDIA Tegra support to QEMU. While
adding SMP support I came across a problem: on Tegra, the secondary CPU
is kept in reset by the clock-and-reset controller (CRC). When bringing
up the secondary CPU, the OS writes a given register in the CRC to
release the
