On Tue, Aug 27, 2013 at 03:35:33PM +0200, Benoît Canet wrote:
> > > > If I understand correctly changing the CPUID L3 cache infos in QEMU
> > > > will change
> > > > the value displayed in the guest /proc/cpuinfo but will not change the
> > > > size of
> > > > the l3 cache used by the hardware. S
On Tue, Aug 27, 2013 at 03:18:16PM +0200, Benoît Canet wrote:
[...]
> > > Do you have some recommandations regarding the other fields of the edx
> > > register ?
> >
> > Probably it will be a good idea to let each CPU model have their own
> > defaults for the cache information.
>
> Do you mean q
> > > If I understand correctly changing the CPUID L3 cache infos in QEMU will
> > > change
> > > the value displayed in the guest /proc/cpuinfo but will not change the
> > > size of
> > > the l3 cache used by the hardware. So I am chasing a cosmetic bug.
> > > If it right ?
> > >
> > Right.
> >
On Tue, Aug 27, 2013 at 04:17:56PM +0300, Gleb Natapov wrote:
> On Tue, Aug 27, 2013 at 03:18:16PM +0200, Benoît Canet wrote:
> >
> > Hello Eduardo,
> >
> > I read a bit about caches on wikipedia.
> >
> > If I understand correctly changing the CPUID L3 cache infos in QEMU will
> > change
> > th
On Tue, Aug 27, 2013 at 03:18:16PM +0200, Benoît Canet wrote:
>
> Hello Eduardo,
>
> I read a bit about caches on wikipedia.
>
> If I understand correctly changing the CPUID L3 cache infos in QEMU will
> change
> the value displayed in the guest /proc/cpuinfo but will not change the size of
> t
Hello Eduardo,
I read a bit about caches on wikipedia.
If I understand correctly changing the CPUID L3 cache infos in QEMU will change
the value displayed in the guest /proc/cpuinfo but will not change the size of
the l3 cache used by the hardware. So I am chasing a cosmetic bug.
If it right ?
On Mon, Aug 26, 2013 at 06:45:27PM +0200, Benoît Canet wrote:
> > Talk to Eduardo since this is related to cpuid configuration and he is
> > an expert.
>
> I found the following in target-i386/cpu.c
>
> case 0x8006:
> /* cache info (L2 cache) */
> *eax = 0;
> *ebx
> Talk to Eduardo since this is related to cpuid configuration and he is
> an expert.
I found the following in target-i386/cpu.c
case 0x8006:
/* cache info (L2 cache) */
*eax = 0;
*ebx = 0x42004200;
*ecx = 0x02008140;
*edx = 0;
break;
>From
On Mon, Aug 26, 2013 at 02:49:41PM +0200, Benoît Canet wrote:
>
> Hi,
>
> Thanks for the answer.
>
> > On Tue, Aug 13, 2013 at 08:17:13PM +0200, Benoît Canet wrote:
> > >
> > > Hi,
> > >
> > > I noticed that the l3 cache size of a guest /proc/cpuinfo is not the same
> > > as
> > > the l3 cach
Hi,
Thanks for the answer.
> On Tue, Aug 13, 2013 at 08:17:13PM +0200, Benoît Canet wrote:
> >
> > Hi,
> >
> > I noticed that the l3 cache size of a guest /proc/cpuinfo is not the same as
> > the l3 cache size of the host.
> >
> > I did not found any references to this in the qemu and KVM cod
On Tue, Aug 13, 2013 at 08:17:13PM +0200, Benoît Canet wrote:
>
> Hi,
>
> I noticed that the l3 cache size of a guest /proc/cpuinfo is not the same as
> the l3 cache size of the host.
>
> I did not found any references to this in the qemu and KVM code.
>
> Is the size of the guest L3 cache fixe
Hi,
I noticed that the l3 cache size of a guest /proc/cpuinfo is not the same as
the l3 cache size of the host.
I did not found any references to this in the qemu and KVM code.
Is the size of the guest L3 cache fixed in hardware ?
Can a patch be written to set it ?
Similarly I noticed that th
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