On 5 June 2011 17:32, Sebastian Huber
wrote:
> On 05/06/11 16:57, Peter Maydell wrote:
>> I agree that the current behaviour is not right. However, to fix
>> this problem you need to work on a larger scale than attempting
>> to apply two line patches which fix your particular use case.
>
> I agree
On 05/06/11 16:57, Peter Maydell wrote:
> On 5 June 2011 15:17, Sebastian Huber
> wrote:
>
>> On 05/06/11 15:44, Peter Maydell wrote:
[...]
>>> (It looks suspiciously as if most of the v7M priority handling
>>> is simply missing from QEMU, ie you have bigger problems than
>>> can be fixed by a
On 5 June 2011 15:17, Sebastian Huber
wrote:
> On 05/06/11 15:44, Peter Maydell wrote:
>> In any case, M profile exception priority handling is sufficiently
>> complicated that any change which only looks at PRIMASK (which is
>> effectively what the change to look at CPSR_I here is doing) is
>> a
On 05/06/11 15:44, Peter Maydell wrote:
> On 5 June 2011 14:06, Sebastian Huber
> wrote:
>
>> I think the interrupt handling logic for ARMv7M is wrong in cpu-exec.c
>> line 470. Please have a look at the attached patch.
>>
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -470,8 +470,8 @@ int cp
On 5 June 2011 14:06, Sebastian Huber
wrote:
> I think the interrupt handling logic for ARMv7M is wrong in cpu-exec.c
> line 470. Please have a look at the attached patch.
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -470,8 +470,8 @@ int cpu_exec(CPUState *env1)
We avoid this by
On 05/06/11 12:31, Sebastian Huber wrote:
> Hello,
>
> how can I disable interrupts on the Cortex M3 based board LM3S6965EVB?
> Even if I set PRIMASK, FAULTMASK and BASEPRI to 1 the SYSTICK interrupt
> handler gets called.
>
> Have a nice day!
>
I think the interrupt handling logic for ARMv7M i
Hello,
how can I disable interrupts on the Cortex M3 based board LM3S6965EVB?
Even if I set PRIMASK, FAULTMASK and BASEPRI to 1 the SYSTICK interrupt
handler gets called.
Have a nice day!
