Re: [Qemu-devel] Cortex-M3: reading NVIC registers causes segfaults

2014-02-18 Thread Peter Maydell
On 18 February 2014 01:14, Andreas Färber wrote: > While first_cpu may help Andreas in his local copy for STM32, that > assumption is not okay in general. The Vybrid VF6 has both a GIC and an > NVIC, so our NVIC code should not make assumptions which CPU it can > access. Do you mean it has an M c

Re: [Qemu-devel] Cortex-M3: reading NVIC registers causes segfaults

2014-02-17 Thread Andreas Färber
Am 17.02.2014 16:18, schrieb Peter Maydell: > On 17 February 2014 14:52, Andreas Galauner wrote: >> I'm currently trying to emulate an ARM Cortex-M3 and I need to debug the >> system using GDB and IDA Pro. The platform is an STM32 and I'm using a >> port from github [1] based on qemu 1.5.1 for tha

Re: [Qemu-devel] Cortex-M3: reading NVIC registers causes segfaults

2014-02-17 Thread Peter Maydell
On 17 February 2014 14:52, Andreas Galauner wrote: > I'm currently trying to emulate an ARM Cortex-M3 and I need to debug the > system using GDB and IDA Pro. The platform is an STM32 and I'm using a > port from github [1] based on qemu 1.5.1 for that. I ported the custom > STM32 code to qemu 1.7.0

[Qemu-devel] Cortex-M3: reading NVIC registers causes segfaults

2014-02-17 Thread Andreas Galauner
Hi qemu developers, I'm currently trying to emulate an ARM Cortex-M3 and I need to debug the system using GDB and IDA Pro. The platform is an STM32 and I'm using a port from github [1] based on qemu 1.5.1 for that. I ported the custom STM32 code to qemu 1.7.0 to have a more recent version to work