> Alexander Graf wrote:
> > They should be atomic. TCG SMP swaps between different vCPUs only
> > after translation blocks are done. In fact, the only way I'm aware
> > of to stop the execution of a TB mid-way is a page fault.
>
> A page fault would interrupt it if the atomic is implemented as
> a
Alexander Graf wrote:
> They should be atomic. TCG SMP swaps between different vCPUs only
> after translation blocks are done. In fact, the only way I'm aware
> of to stop the execution of a TB mid-way is a page fault.
A page fault would interrupt it if the atomic is implemented as
a read followed
On 23.04.2010, at 19:27, Jakub Jermar wrote:
> Hello,
>
> is it at least theoretically possible that the guest atomic instructions
> (e.g. XCHG,
> LOCK CMPXCHG) on target-i386 are somehow not atomic when simulated/translated
> by Qemu?
>
> I am observing a problem with one of my HelenOS/ia32
Hello,
is it at least theoretically possible that the guest atomic instructions (e.g.
XCHG,
LOCK CMPXCHG) on target-i386 are somehow not atomic when simulated/translated
by Qemu?
I am observing a problem with one of my HelenOS/ia32 builds which suggests me
that for
some reason HelenOS spinlock
