On Fri, 09 Mar 2018 13:49:57 PST (-0800), c...@braap.org wrote:
On Fri, Mar 09, 2018 at 11:34:56 +, Michael Clark wrote:
Isn't Cc'ing riscv-patches an obvious use case for using the --cc flag?
(BTW You can add as many --cc's as you want, and these apply to all patches
in a series.)
FWIW, th
On Fri, Mar 09, 2018 at 11:34:56 +, Michael Clark wrote:
> BTW how does one hide signed-off-by or cc email addresses with the
> git-send-email workflow?
You just don't.
> Seems like editing the patch after git format-patch is likely the only way
> around for contributors whose wishes I might
BTW I was looking at the IEEE-754 2008 minNum/maxNum code today (the reason
I was running riscv-tests) so that I could forward port the patch to add
IEEE-754 201x minimumNumber/maximumNumber (as there are two pairs of
distinct IEEE-754 functions which have distinct behaviour with respect to
sNaN) a
On 9 March 2018 at 13:58:06, Michael Clark (m...@sifive.com) wrote:
> ... Hopefully we’ll have binary images for the various artefacts
> on the Releases section on all of the riscv repos,
> ...
> It will be great when binaries are included with the GitHub Releases/tags
> assuming we use GitHub Rel
On Sat, 10 Mar 2018 at 12:30 AM, Philippe Mathieu-Daudé
wrote:
> Hi Michael,
>
> On 03/09/2018 12:17 PM, Michael Clark wrote:
> > On Fri, 9 Mar 2018 at 11:45 PM, Peter Maydell
> > wrote:
> >
> >> On 9 March 2018 at 04:22, Michael Clark wrote:
> >>> I need to dig into this. I'll need to take the
On Sat, 10 Mar 2018 at 12:17 AM, Michael Clark wrote:
> On Fri, 9 Mar 2018 at 11:45 PM, Peter Maydell
> wrote:
>
>> On 9 March 2018 at 04:22, Michael Clark wrote:
>> > I need to dig into this. I'll need to take the assertions out, or run
>> with
>> > tracing to see which fcvt test is triggering
Hi Michael,
On 03/09/2018 12:17 PM, Michael Clark wrote:
> On Fri, 9 Mar 2018 at 11:45 PM, Peter Maydell
> wrote:
>
>> On 9 March 2018 at 04:22, Michael Clark wrote:
>>> I need to dig into this. I'll need to take the assertions out, or run
>> with
>>> tracing to see which fcvt test is triggerin
On Fri, 9 Mar 2018 at 11:45 PM, Peter Maydell
wrote:
> On 9 March 2018 at 04:22, Michael Clark wrote:
> > I need to dig into this. I'll need to take the assertions out, or run
> with
> > tracing to see which fcvt test is triggering this unreachable piece of
> > code. FYI. I can look into it.
>
>
On 9 March 2018 at 04:22, Michael Clark wrote:
> I need to dig into this. I'll need to take the assertions out, or run with
> tracing to see which fcvt test is triggering this unreachable piece of
> code. FYI. I can look into it.
> ERROR:/Users/mclark/src/sifive/riscv-qemu/fpu/softfloat.c:1374:ro
I need to dig into this. I'll need to take the assertions out, or run with
tracing to see which fcvt test is triggering this unreachable piece of
code. FYI. I can look into it.
$ sh run-riscv-tests.sh
rv64ua-v-amoadd_d
rv64ua-v-amoadd_w
rv64ua-v-amoand_d
rv64ua-v-amoand_w
rv64ua-v-amomax_d
rv64ua-
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