Re: [Qemu-devel] ARM64 Interrupt handling on QEMU

2018-03-15 Thread Peter Maydell
On 15 March 2018 at 20:24, Brijen Raval wrote: > On Thu, Mar 15, 2018 at 2:59 AM Peter Maydell > wrote: >> Exception 5 is IRQ. (These numbers are all internal to QEMU, and >> don't have any architectural or guest-visible relevance. They're >> the EXCP_* constants defined at the top of target/arm/

Re: [Qemu-devel] ARM64 Interrupt handling on QEMU

2018-03-15 Thread Brijen Raval
On Thu, Mar 15, 2018 at 2:59 AM Peter Maydell wrote: > On 15 March 2018 at 03:07, Brijen Raval wrote: > > I am booting up a custom kernel on QEMU ARM64, upon completion of its > > initial boot up it looks like it enters the arch_idle() state > > > > I enabled the -d int logging to understand wha

Re: [Qemu-devel] ARM64 Interrupt handling on QEMU

2018-03-15 Thread Peter Maydell
On 15 March 2018 at 03:07, Brijen Raval wrote: > I am booting up a custom kernel on QEMU ARM64, upon completion of its > initial boot up it looks like it enters the arch_idle() state > > I enabled the -d int logging to understand what is going on, I see the > following repeated many times continuo

[Qemu-devel] ARM64 Interrupt handling on QEMU

2018-03-14 Thread Brijen Raval
I am booting up a custom kernel on QEMU ARM64, upon completion of its initial boot up it looks like it enters the arch_idle() state I enabled the -d int logging to understand what is going on, I see the following repeated many times continuosly here after Taking exception 5 [IRQ] ...from EL1 to E