On Sunday 10 September 2006 17:46, Fabrice Bellard wrote:
> Note that QEMU supports specific unaligned access handling when using
> the softmmu code. It is possible to implement the ARM specific unaligned
> accesses without slowing down the aligned case. See the mips case with
> do_unaligned_access
Note that QEMU supports specific unaligned access handling when using
the softmmu code. It is possible to implement the ARM specific unaligned
accesses without slowing down the aligned case. See the mips case with
do_unaligned_access().
Regards,
Fabrice.
Justin Fletcher wrote:
On Sun, 10 Se
On Sun, 10 Sep 2006, Paul Brook wrote:
---8<---
if (n != 1)
gen_op_addl_T1_im(-((n - 1) * 4));
}
}
j = 0;
/* Insert something like gen_op_bicl_T1_im(3); here */
for(i=0;i
> ---8<---
> if (n != 1)
> gen_op_addl_T1_im(-((n - 1) * 4));
> }
> }
> j = 0;
> /* Insert something like gen_op_bicl_T1_im(3); here */
> for(i=0;i<16;i++) {
>
Hiya,
I have found a bug in the implementation of the load/store multiple
instructions in ARM (LDM and STM). These are defined in the ARM ARM to
ignore bits 0 and 1 of the address when the load takes place - that is the
base register for these operations is always treated as a 32bit aligned
v
