On Sat, Jun 16, 2012 at 9:09 PM, Peter Maydell wrote:
> On 16 June 2012 18:37, Christoffer Dall wrote:
>>> On 22 May 2012 13:22, Peter Maydell wrote:
Historically for QEMU we haven't implemented TrustZone support even
though we claim to emulate CPUs that provide it. Instead we provide
Hm, one memory space, but what about write access restrictions, e.g.
for Non-Secure or Secure worlds for some memory addresses/blocks?
Best regards,
Anton Kochkov.
On Sat, Jun 16, 2012 at 9:37 PM, Christoffer Dall
wrote:
>> On 22 May 2012 13:22, Peter Maydell wrote:
>>> Historically for QEMU w
On 16 June 2012 18:37, Christoffer Dall wrote:
>> On 22 May 2012 13:22, Peter Maydell wrote:
>>> Historically for QEMU we haven't implemented TrustZone support even
>>> though we claim to emulate CPUs that provide it. Instead we provide a
>>> CPU which mostly looks like a variant of the real thin
> On 22 May 2012 13:22, Peter Maydell wrote:
>> Historically for QEMU we haven't implemented TrustZone support even
>> though we claim to emulate CPUs that provide it. Instead we provide a
>> CPU which mostly looks like a variant of the real thing without the
>> TrustZone feature. We then bolt on
Andreas pointed out that I should have cc'd Johannes here. Sorry
for forgetting that.
-- PMM
On 22 May 2012 13:22, Peter Maydell wrote:
> Historically for QEMU we haven't implemented TrustZone support even
> though we claim to emulate CPUs that provide it. Instead we provide a
> CPU which mostly
Historically for QEMU we haven't implemented TrustZone support even
though we claim to emulate CPUs that provide it. Instead we provide a
CPU which mostly looks like a variant of the real thing without the
TrustZone feature. We then bolt on a few extra cp15 registers (eg the
SCR) as a pragmatic mov
