> However, we have seen that the condition bits in CPSR differers compared to
> one other arm instruction set simulator, running the same binary. This
> indicate for us that there might be something wrong i QEMU (translate.c
> op.c for ARM). However, it is not proven yet.
The only restriction it t
s. I
had some problems sending my mail.
/Torbjörn
Från: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] För
Torbjörn Andersson
Skickat: den 21 november 2006 22:16
Till: qemu-devel@nongnu.org
Ämne: [Qemu-devel] ARM CPSR and conditional instructions
Hello qemu developers!
I´m using QEMU for some A
jörn
> >
> > Från: [EMAIL PROTECTED]
> > [mailto:[EMAIL PROTECTED] För
> > Torbjörn Andersson
> > Skickat: den 21 november 2006 22:16
> > Till: qemu-devel@nongnu.org
> > Ämne: [Qemu-devel] ARM CPSR and conditional instructions
> >
> > Hello qem
: qemu-devel@nongnu.org
> Ämne: [Qemu-devel] ARM CPSR and conditional instructions
>
> Hello qemu developers!
>
> I´m using QEMU for some ARM debugging and I have som questions
> regardning the CPSR register. I get the feeling that the CPSR
> condition code bits, represent
Im sorry for spamming you mailing list with my duplicate posts. I had some
problems sending my mail.
/Torbjörn
_
Från: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] För
Torbjörn Andersson
Skickat: den 21 november 2006 22:16
Till: qemu-devel@nongnu.org
Ämne: [Qemu-devel] ARM CPSR and
Hello qemu developers!
I´m using QEMU for some ARM debugging and I have som questions regardning
the CPSR register. I get the feeling that the CPSR condition code bits,
representing the results from the ALU, are not maintained at all points. Is
the JIT in QEMU tailored in any way towards GCC outpu
Hello qemu developers!
I´m using QEMU for some ARM debugging and I have som questions regardning
the CPSR register. I get the feeling that the CPSR condition code bits,
representing the results from the ALU, are not maintained at all points. Is
the JIT in QEMU tailored in any way towards GCC outpu
