Bastian Koppelmann writes:
> On 07/25/2017 06:37 PM, Bruce Hoult wrote:
>> Do you have any good estimates for how much of the execution time is
>> typically spent in instruction decode?
>>
>> RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing
>> something right!
>>
>> (I suspect
> On 27 Jul 2017, at 8:58 AM, kr...@berkeley.edu wrote:
>
>
> Given that one of the goals of RISC-V is extensibility, it would be
> nice if the QEMU port was done in a way to make it easier to extend by
> third parties, including other automated tools. I'm sure that, over
> time, the preprocess
Given that one of the goals of RISC-V is extensibility, it would be
nice if the QEMU port was done in a way to make it easier to extend by
third parties, including other automated tools. I'm sure that, over
time, the preprocessor can be improved to automatically incorporate
optimizations for bett
On Wed, Jul 26, 2017 at 02:00:14PM +0200, Bastian Koppelmann wrote:
> Hi Samuel,
>
> On 07/25/2017 04:31 PM, Samuel Falvo II wrote:
> > For those of us who are not in the know, how does target/s390 decoding work?
>
> sorry about that. I was going into this with a QEMU-dev mindset :)
>
> The basi
On Tue, Jul 25, 2017 at 9:37 AM, Bruce Hoult wrote:
> Do you have any good estimates for how much of the execution time is
> typically spent in instruction decode?
>
> RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing something
> right!
>
> (I suspect it's probably mostly the lack
Hi Samuel,
On 07/25/2017 04:31 PM, Samuel Falvo II wrote:
> For those of us who are not in the know, how does target/s390 decoding work?
sorry about that. I was going into this with a QEMU-dev mindset :)
The basic idea of s390x is to have every instruction + instruction
formats specified in file
On 07/25/2017 06:37 PM, Bruce Hoult wrote:
> Do you have any good estimates for how much of the execution time is
> typically spent in instruction decode?
>
> RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing
> something right!
>
> (I suspect it's probably mostly the lack of need
Do you have any good estimates for how much of the execution time is
typically spent in instruction decode?
RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing
something right!
(I suspect it's probably mostly the lack of needing to emulate condition
codes)
On Tue, Jul 25, 2017 at
For those of us who are not in the know, how does target/s390 decoding work?
I've maintained a 65816 emulator
(https://bitbucket.org/kc5tja/lib65816/src) which also uses a giant
case construct. This method is used because it's fast. Any
alternative approaches you decide to take might well work a
