Blue Swirl a écrit :
> Hi,
>
> I can't reproduce the problem with attached test program. Also the generated
> ops look just fine:
>
[snip]
>
> Can you describe how to reproduce the bug?
>
Well I also have difficulties to reproduce it with a simple program. I
have detected it while trying to
Hi,
I can't reproduce the problem with attached test program. Also the generated
ops look just fine:
IN:
0x00010074: sethi %hi(0x2), %g3
0x00010078: or %g3, 0xa0, %g3 ! 0x200a0
0x0001007c: mov -1, %g1
0x00010080: mov -1, %g2
0x00010084: tst %g0
0x00010088: bne 0x10094
0x0001008
On Wed, Mar 21, 2007 at 09:34:46PM +0100, Aurelien Jarno wrote:
> Blue Swirl a écrit :
> >>From my tests, it seems that std in a delayed branch slot occurs a
> >> hundred of time during a boot, so not a lot. Adding a new field to the
> >> CPU structure would probably decrease the performances (exce
Blue Swirl a écrit :
>>From my tests, it seems that std in a delayed branch slot occurs a
>> hundred of time during a boot, so not a lot. Adding a new field to the
>> CPU structure would probably decrease the performances (except on
>> hosts with a lot of registers). Therefore I am proposing someth
From my tests, it seems that std in a delayed branch slot occurs a
hundred of time during a boot, so not a lot. Adding a new field to the
CPU structure would probably decrease the performances (except on
hosts with a lot of registers). Therefore I am proposing something like
that (currently for st
On Wed, Mar 21, 2007 at 07:42:20PM +0100, Blue Swirl wrote:
> >I have noticed that the branches have some problem on the sparc target
> >in very rare conditions. This happens when a store double instruction
> >(std) is used in the delay slot, as in the following test:
> >
> > tst %g0
> > bne 9b
I have noticed that the branches have some problem on the sparc target
in very rare conditions. This happens when a store double instruction
(std) is used in the delay slot, as in the following test:
tst %g0
bne 9b5d8
std %o2, [ %o1 ]
Inserting a nop between bne and std "fixes" the prob
Hi all,
I have noticed that the branches have some problem on the sparc target
in very rare conditions. This happens when a store double instruction
(std) is used in the delay slot, as in the following test:
tst %g0
bne 9b5d8
std %o2, [ %o1 ]
Inserting a nop between bne and std "fixes"
