2012/2/8 Paul Brook
> > > - When are interrupts raised. You mention a user specified match
> value.
> > > Do we also get an interrupt on wraparound?
> >
> > Yes, an interrupts occur on wrap around of the 16 bit timer value. There
> > are three match registers which correspond to three more
> >
> > - When are interrupts raised. You mention a user specified match value.
> > Do we also get an interrupt on wraparound?
>
> Yes, an interrupts occur on wrap around of the 16 bit timer value. There
> are three match registers which correspond to three more
> (separately maskable) interrupts w
2012/2/8 Paul Brook
> > > > Implemented cadence Triple Timer Counter (TCC)
> > >
> > > It looks like you're implementing a periodic timer as sequence of
> chained
> > > oneshot timers. This is a bad idea. In qemu interrupt latency may be
> > > high,
> > > so you're likely to suffer from signifi
> > > Implemented cadence Triple Timer Counter (TCC)
> >
> > It looks like you're implementing a periodic timer as sequence of chained
> > oneshot timers. This is a bad idea. In qemu interrupt latency may be
> > high,
> > so you're likely to suffer from significant time skew.
> >
> Ok, I could
2012/2/7 Paul Brook
> > Implemented cadence Triple Timer Counter (TCC)
>
> It looks like you're implementing a periodic timer as sequence of chained
> oneshot timers. This is a bad idea. In qemu interrupt latency may be
> high,
> so you're likely to suffer from significant time skew.
>
> Ok, I
> Implemented cadence Triple Timer Counter (TCC)
It looks like you're implementing a periodic timer as sequence of chained
oneshot timers. This is a bad idea. In qemu interrupt latency may be high,
so you're likely to suffer from significant time skew.
Paul
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite
Signed-off-by: John Linn
---
changes from v1
refactored event driven code
marked vmsd as unmigratable
Makefile.target |1 +
hw/cadence_ttc.c | 399 ++
