On Wed, Jul 15, 2015 at 06:28:54PM +0100, Varun Sethi wrote:
> > > > On Fri, Jun 12, 2015 at 03:20:04PM +0100, Baptiste Reynal wrote:
> > > > > The ARM SMMU has support for 2-stages address translations,
> > > > > allowing a virtual address to be translated at two levels:
> > > > > - Stage 1 transl
Hi Will,
> -Original Message-
> From: Will Deacon [mailto:will.dea...@arm.com]
> Sent: Tuesday, July 14, 2015 4:34 PM
> To: Sethi Varun-B16395
> Cc: Baptiste Reynal; io...@lists.linux-foundation.org;
> t...@virtualopensystems.com; qemu-devel@nongnu.org
> Subject: Re: [RFC 0/6] vSMMU initia
Hi Baptiste,
> -Original Message-
> From: Baptiste Reynal [mailto:b.rey...@virtualopensystems.com]
> Sent: Wednesday, July 15, 2015 7:08 PM
> To: Will Deacon
> Cc: Sethi Varun-B16395; io...@lists.linux-foundation.org;
> t...@virtualopensystems.com; qemu-devel@nongnu.org
> Subject: Re: [RFC
On Wed, Jul 15, 2015 at 02:38:15PM +0100, Baptiste Reynal wrote:
> On Tue, Jul 14, 2015 at 1:04 PM, Will Deacon wrote:
> > I think SMMUv3 is *far* more amenable to the vSMMU approach, largely
> > because it moves many of the data structures into memory, but also because
> > it has support for thin
On Tue, Jul 14, 2015 at 1:04 PM, Will Deacon wrote:
> On Tue, Jul 14, 2015 at 03:21:03AM +0100, Varun Sethi wrote:
>> Hi Will,
>
> Hi Varun,
>
>> > On Fri, Jun 12, 2015 at 03:20:04PM +0100, Baptiste Reynal wrote:
>> > > The ARM SMMU has support for 2-stages address translations, allowing a
>> > >
On Tue, Jul 14, 2015 at 03:21:03AM +0100, Varun Sethi wrote:
> Hi Will,
Hi Varun,
> > On Fri, Jun 12, 2015 at 03:20:04PM +0100, Baptiste Reynal wrote:
> > > The ARM SMMU has support for 2-stages address translations, allowing a
> > > virtual address to be translated at two levels:
> > > - Stage 1
Hi Will,
> -Original Message-
> From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
> boun...@lists.linux-foundation.org] On Behalf Of Will Deacon
> Sent: Friday, June 12, 2015 7:53 PM
> To: Baptiste Reynal
> Cc: io...@lists.linux-foundation.org; t...@virtualopensystems.com;
> qe
On Fri, Jun 12, 2015 at 03:20:04PM +0100, Baptiste Reynal wrote:
> The ARM SMMU has support for 2-stages address translations, allowing a virtual
> address to be translated at two levels:
> - Stage 1 translates a virtual address (VA) into an intermediate physical
> address (IPA)
> - Stage 2 transla
The ARM SMMU has support for 2-stages address translations, allowing a virtual
address to be translated at two levels:
- Stage 1 translates a virtual address (VA) into an intermediate physical
address (IPA)
- Stage 2 translates an IPA into a physical address (PA)
Will Deacon introduced a virtual S
