On Wed, Aug 31, 2016 at 08:59:41AM +0800, Longpeng (Mike) wrote:
[...]
> >> -/* No L3 cache: */
> >> -#define L3_SIZE_KB 0 /* disabled */
> >> -#define L3_ASSOCIATIVITY 0 /* disabled */
> >> -#define L3_LINES_PER_TAG 0 /* disabled */
> >> -#define L3_LINE_SIZE 0 /*
Hi Eduardo，
On 2016/8/30 22:25, Eduardo Habkost wrote:
> On Mon, Aug 29, 2016 at 09:17:02AM +0800, Longpeng (Mike) wrote:
>> This patch presents virtual L3 cache info for virtual cpus.
>
> Just changing the L3 cache size in the CPUID code will make
> guests see a different cache topology after u
On Mon, Aug 29, 2016 at 09:17:02AM +0800, Longpeng (Mike) wrote:
> This patch presents virtual L3 cache info for virtual cpus.
Just changing the L3 cache size in the CPUID code will make
guests see a different cache topology after upgrading QEMU (even
on live migration). If you want to change the
This patch presents virtual L3 cache info for virtual cpus.
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cach
