Hi Edgar,
On 3/4/19 11:29 AM, Edgar E. Iglesias wrote:
> Hi Damien and others,
>
> A few questions from my side.
>
> We sometimes see that wires from generic GPIO blocks get connected to reset
> inputs.
> This happens both to off-chip perihperals but we also see it on-chip.
>
> To avoid having
On 3/1/19 5:52 PM, Peter Maydell wrote:
> On Fri, 1 Mar 2019 at 15:34, Damien Hedde wrote:
>>
>> On 3/1/19 12:43 PM, Peter Maydell wrote:
>>> On Mon, 25 Feb 2019 at 10:49, Damien Hedde
>>> wrote:
I had more thought about the reset problem and what we want to achieve
(add power gatin
Hi Damien and others,
A few questions from my side.
We sometimes see that wires from generic GPIO blocks get connected to reset
inputs.
This happens both to off-chip perihperals but we also see it on-chip.
To avoid having GPIO modules know that some of their outputs are being used as
reset sign
On Sun, Mar 03, 2019 at 10:59:30AM +, Peter Maydell wrote:
> On Sat, 2 Mar 2019 at 19:41, Philippe Mathieu-Daudé wrote:
> >
> > Hi Damien,
> >
> > On 3/1/19 5:52 PM, Peter Maydell wrote:
> > > On Fri, 1 Mar 2019 at 15:34, Damien Hedde
> > > wrote:
> > >> On 3/1/19 12:43 PM, Peter Maydell wro
On Sat, 2 Mar 2019 at 19:41, Philippe Mathieu-Daudé wrote:
>
> Hi Damien,
>
> On 3/1/19 5:52 PM, Peter Maydell wrote:
> > On Fri, 1 Mar 2019 at 15:34, Damien Hedde
> > wrote:
> >> On 3/1/19 12:43 PM, Peter Maydell wrote:
> >>> In my design the only thing that I thought would happen in phase 3
>
Hi Damien,
On 3/1/19 5:52 PM, Peter Maydell wrote:
> On Fri, 1 Mar 2019 at 15:34, Damien Hedde wrote:
>> On 3/1/19 12:43 PM, Peter Maydell wrote:
>>> In my design the only thing that I thought would happen in phase 3
>>> was the "clear the resetting flag", but you've moved that to RELEASE.
>>> Wh
On Fri, 1 Mar 2019 at 15:34, Damien Hedde wrote:
>
> On 3/1/19 12:43 PM, Peter Maydell wrote:
> > On Mon, 25 Feb 2019 at 10:49, Damien Hedde
> > wrote:
> >> I had more thought about the reset problem and what we want to achieve
> >> (add power gating and clock support).
> >> Feel free to comment
On 3/1/19 12:43 PM, Peter Maydell wrote:
> On Mon, 25 Feb 2019 at 10:49, Damien Hedde wrote:
>> I had more thought about the reset problem and what we want to achieve
>> (add power gating and clock support).
>> Feel free to comment. I'll start to implement this and send a first
>> version with a r
On Mon, 25 Feb 2019 at 10:49, Damien Hedde wrote:
> I had more thought about the reset problem and what we want to achieve
> (add power gating and clock support).
> Feel free to comment. I'll start to implement this and send a first
> version with a reroll of everything when it's ready.
I general
On Mon, 25 Feb 2019 at 10:49, Damien Hedde wrote:
>
> Hi,
>
> I had more thought about the reset problem and what we want to achieve
> (add power gating and clock support).
> Feel free to comment. I'll start to implement this and send a first
> version with a reroll of everything when it's ready.
Hi,
I had more thought about the reset problem and what we want to achieve
(add power gating and clock support).
Feel free to comment. I'll start to implement this and send a first
version with a reroll of everything when it's ready.
# CONTEXT
We want to model the clock distribution between devi
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