On 10/20/2017 06:57 PM, Richard Henderson wrote:
> All that said, this looks very readable. Thank you.
>
Thanks for your great feedback. I think most of them are not hard to
implement. However I might need some time for that :)
Cheers,
Bastian
On 10/20/2017 06:46 AM, Bastian Koppelmann wrote:
> The RISC-V data in YAML consists of:
>
> 1) prefixes
> 2) instruction formats
> 3) instruction specification using the data of 1) and 2)
>
> 1) prefixes have:
>- name
>- bitmask that identifies instructions belonging to it
>- length
Hi QEMU and RISC-V folks,
I asked you for feedback some while ago regarding a modular RISC-V QEMU
target (see discussion [1]). I tried getting it to work with the good
old C preprocessor and quickly realized that it is too limiting. Instead
I created a data-driven decoder generator written in pyth
