Hello all,
This patch tries to solve a problem whereby real AMD IOMMUs exhibit both PCI
and Platform device properties. AMD IOMMU properties that conflict with
conventional PCI devices' features include the fact that its not a BusMaster
device and reserves MMIO region without a BAR register amo
Hello all,
This patch tries to solve a problem whereby real AMD IOMMUs exhibit both PCI
and Platform device properties. AMD IOMMU properties that conflict with
conventional PCI devices' features include the fact that its not a BusMaster
device, reserves MMIO region without a BAR register.
Ther
