Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define

2017-02-12 Thread David Gibson
On Fri, Feb 10, 2017 at 04:25:52PM +1100, Suraj Jitindar Singh wrote: > The DPFD field in the LPCR is 3 bits wide. This has always been defined > as 0x3 << shift which indicates a 2 bit field, which is incorrect. > Correct this. > > Signed-off-by: Suraj Jitindar Singh Since this is a correct fix

[Qemu-devel] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define

2017-02-09 Thread Suraj Jitindar Singh
The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b