Hi,
Your series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [QEMU, PATCH] x86: implement la57 paging mode
Type: series
Message-id: 20161208162150.148763-2-kirill.shute...@linux.intel.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
The new paging more is extension of IA32e mode with more additional page
table level.
It brings support of 57-bit vitrual address space (128PB) and 52-bit
physical address space (4PB).
The structure of new page table level is identical to pml4.
The feature is enumerated with CPUID.(EAX=07H, ECX=
