OK, this is what I've come up with. Dunno whether it's right or not
-- the object model is decoupled from the memory model, so there's no
straightforward way to override just a few of the registers.
At this stage this is just for comment, as I don't really have that
much of a clue about how the
Am 06.08.2013 02:00, schrieb pe...@chubb.wattle.id.au:
>> "Andreas" == Andreas Färber writes:
>
> Andreas> Am 05.08.2013 11:18, schrieb Peter Maydell:
>>> On 5 August 2013 02:21, Peter Chubb
>>> wrote:
Reads to unassigned memory now return non-zero (since patch
9b8c69243585). This
> "Andreas" == Andreas Färber writes:
Andreas> Peter Ch., if you know the exact differences, why don't you
Andreas> just derive an imx-l2cc type (or so) derived from ARM's type,
Andreas> overriding the values mentioned above? Sounds trivial to me.
For what it's worth, here's a diff between
> "Andreas" == Andreas Färber writes:
Andreas> Am 05.08.2013 11:18, schrieb Peter Maydell:
>> On 5 August 2013 02:21, Peter Chubb
>> wrote:
>>> Reads to unassigned memory now return non-zero (since patch
>>> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
>>> cache controlle
> "Peter" == Peter Maydell writes:
Peter> On 5 August 2013 02:21, Peter Chubb
Peter> wrote:
>> Reads to unassigned memory now return non-zero (since patch
>> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
>> cache controller --- they poll forever waiting for the L2CC cache
Am 05.08.2013 11:18, schrieb Peter Maydell:
> On 5 August 2013 02:21, Peter Chubb wrote:
>> Reads to unassigned memory now return non-zero (since patch
>> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
>> cache controller --- they poll forever waiting for the L2CC cache
>> invali
On 5 August 2013 02:21, Peter Chubb wrote:
> Reads to unassigned memory now return non-zero (since patch
> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
> cache controller --- they poll forever waiting for the L2CC cache
> invalidate regsiter to be zero.
That commit claims it w
Reads to unassigned memory now return non-zero (since patch
9b8c69243585). This breaks guests runnong on i.MX31 that use the
cache controller --- they poll forever waiting for the L2CC cache
invalidate regsiter to be zero.
This patch adds in an L2 cache controller. It's not quite right ---
it r
