Re: [Qemu-devel] [PULL v2 00/18] tcg queued patches

2016-09-12 Thread Richard Henderson
On 09/08/2016 11:51 PM, Richard Henderson wrote: On 09/08/2016 05:06 PM, Pranith Kumar wrote: What error are you seeing? Something else entirely. My alpha kernel is crashing. I thought it was something in this patch set, after I rebased, but now I can see it's in HEAD too. I'll have to spen

Re: [Qemu-devel] [PULL v2 00/18] tcg queued patches

2016-09-08 Thread Richard Henderson
On 09/08/2016 05:06 PM, Pranith Kumar wrote: What error are you seeing? Something else entirely. My alpha kernel is crashing. I thought it was something in this patch set, after I rebased, but now I can see it's in HEAD too. I'll have to spend some time tracking it down. r~

Re: [Qemu-devel] [PULL v2 00/18] tcg queued patches

2016-09-08 Thread Pranith Kumar
On Thu, Sep 8, 2016 at 7:49 PM, Pranith Kumar wrote: >> On 09/08/2016 10:15 AM, Richard Henderson wrote: >> Ho hum. I think I've mucked something up here too. >> Please ignore this pull. >> > > I think I found the error. It looks like the fence optimization patch > is causing the error. > > I wil

Re: [Qemu-devel] [PULL v2 00/18] tcg queued patches

2016-09-08 Thread Pranith Kumar
On Thu, Sep 8, 2016 at 4:38 PM, Richard Henderson wrote: > On 09/08/2016 10:15 AM, Richard Henderson wrote: >> >> Three unrelated patches and Pranith's memory barrier patch sets. >> >> The alignment patch is in support of Sparc's ldf instructions: >> 8 and 16-byte memory operations that require on

Re: [Qemu-devel] [PULL v2 00/18] tcg queued patches

2016-09-08 Thread Richard Henderson
On 09/08/2016 10:15 AM, Richard Henderson wrote: Three unrelated patches and Pranith's memory barrier patch sets. The alignment patch is in support of Sparc's ldf instructions: 8 and 16-byte memory operations that require only 4-byte alignment. It's just as easy to support this kind of misalignm

[Qemu-devel] [PULL v2 00/18] tcg queued patches

2016-09-08 Thread Richard Henderson
Three unrelated patches and Pranith's memory barrier patch sets. The alignment patch is in support of Sparc's ldf instructions: 8 and 16-byte memory operations that require only 4-byte alignment. It's just as easy to support this kind of misalignment as any other. As mentioned in the commit, we'd