Re: [Qemu-devel] [PULL 01/12] target-ppc: optimize cmp translation

2018-01-18 Thread David Gibson
On Thu, Jan 18, 2018 at 05:36:40PM +0100, Paolo Bonzini wrote: > On 08/01/2018 06:53, David Gibson wrote: > > From: "pbonz...@redhat.com" > > > > We know that only one bit (in addition to SO) is going to be set in > > the condition register, so do two movconds instead of three setconds, > > three

Re: [Qemu-devel] [PULL 01/12] target-ppc: optimize cmp translation

2018-01-18 Thread Paolo Bonzini
On 08/01/2018 06:53, David Gibson wrote: > From: "pbonz...@redhat.com" > > We know that only one bit (in addition to SO) is going to be set in > the condition register, so do two movconds instead of three setconds, > three shifts and two ORs. > > For ppc64-linux-user, the code size reduction is

[Qemu-devel] [PULL 01/12] target-ppc: optimize cmp translation

2018-01-07 Thread David Gibson
From: "pbonz...@redhat.com" We know that only one bit (in addition to SO) is going to be set in the condition register, so do two movconds instead of three setconds, three shifts and two ORs. For ppc64-linux-user, the code size reduction is around 5% and the performance improvement slightly less