Re: [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case

2018-04-26 Thread Alistair Francis
On Wed, Apr 25, 2018 at 4:56 PM Michael Clark wrote: > satp is WARL so it should not trap on illegal writes, rather > it can be hardwired to zero and silently ignore illegal writes. > It seems the RISC-V WARL behaviour is preferred to having to > trap overhead versus simply reading back the valu

[Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case

2018-04-25 Thread Michael Clark
satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and